High-speed serial data transceiver and related methods
First Claim
1. A communication device on an integrated circuit (IC) chip, comprising:
- a master signal generator adapted to generate a master timing signal;
a receive-lane adapted to receive an analog serial data signal and including a sampling signal generator adapted to generate multiple time-staggered sampling signals based on the master timing signal, and multiple data paths each adapted to sample the serial data signal in accordance with a corresponding one of the time-staggered sampling signals, thereby producing multiple time-staggered data sample streams; and
a data demultiplexer module adapted to time-deskew and demultiplex the multiple time-staggered data streams.
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Accused Products
Abstract
A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.
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Citations
32 Claims
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1. A communication device on an integrated circuit (IC) chip, comprising:
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a master signal generator adapted to generate a master timing signal;
a receive-lane adapted to receive an analog serial data signal and including a sampling signal generator adapted to generate multiple time-staggered sampling signals based on the master timing signal, and multiple data paths each adapted to sample the serial data signal in accordance with a corresponding one of the time-staggered sampling signals, thereby producing multiple time-staggered data sample streams; and
a data demultiplexer module adapted to time-deskew and demultiplex the multiple time-staggered data streams. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A communication device on an integrated circuit (IC) chip and configured to receive multiple serial data signals, comprising:
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a master timing generator adapted to generate a master timing signal;
multiple receive-lanes each configured to receive an associated one of the multiple serial data signals, each receive-lane including a phase interpolator adapted to produce a sampling signal having an interpolated phase, and a data path adapted to sample and quantize the associated serial data signal in accordance with the sampling signal; and
an interpolator control module coupled to each receive-lane, the interpolator control module being adapted to cause the phase interpolator in each receive-lane to rotate the interpolated phase of the sampling signal in the receive-lane at a rate corresponding to a frequency offset between the sampling signal and the serial data signal associated with the receive-lane so as to reduce the frequency offset between the sampling signal and the serial data signal. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method in a communication device, comprising:
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(a) generating a master timing signal;
(b) generating multiple time-staggered sampling signals based on the master timing signal;
(c) sampling a received, analog serial data signal in accordance with each of the multiple time-staggered sampling signals, thereby producing multiple time-staggered data sample streams; and
(d) time-deskewing the multiple time-staggered data streams;
(e) demultiplexing multiple time-deskewed data streams produced in step (d). - View Dependent Claims (21, 22, 23, 24, 25, 26, 28, 29, 30, 31)
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27. In a communication device configured to receive multiple serial data signals, a method, comprising:
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(a) generating a master timing signal;
(b) deriving multiple sampling signals based on the master timing signal, each of the multiple sampling signals being associated with one of the multiple serial data signals, each of the sampling signals having an interpolated phase, and (c) sampling and quantizing each of the multiple serial data signals according to the associated one of the sampling signals; and
(d) rotating the interpolated phase of each sampling signal at a rate corresponding to a frequency offset between the sampling signal and the serial data signal associated with the receive-lane so as to reduce the frequency offset between the sampling signal and the serial data signal.
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32. A system for routing high data rate analog data signals, comprising:
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a backplane having a plurality of signal paths; and
at least one interface board coupled to the backplane, the interface board including a plurality of receivers coupled to the backplane signal paths, each said receiver including a phase interpolator adapted to derive a sampling signal having an interpolated phase and used to sample an associated analog data signal received from said associated backplane signal path.
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Specification