Scalable architecture based on single-chip multiprocessing
First Claim
1. A chip-multiprocessing system with scalable architecture, comprising on a single chip:
- a plurality of processor cores;
a two-level cache hierarchy including a pair of instruction and data caches for, and private to, each processor core, the pair being first level caches, and a second level cache with a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores, the second level cache being modular with a plurality of interleaved modules;
one or more memory controllers capable of operatively communicating with the two-level cache hierarchy and with an off-chip memory;
a cache coherence protocol;
one or more coherence protocol engines;
an intra-chip switch; and
an interconnect subsystem.
5 Assignments
0 Petitions
Accused Products
Abstract
A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads. A showcase example of the chip-multiprocessing system, called the PIRANHA™ system, is a highly integrated processing node with eight simpler ALPHA™ processor cores. A method for scalable chip-multiprocessing is also provided.
-
Citations
31 Claims
-
1. A chip-multiprocessing system with scalable architecture, comprising on a single chip:
-
a plurality of processor cores;
a two-level cache hierarchy including a pair of instruction and data caches for, and private to, each processor core, the pair being first level caches, and a second level cache with a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores, the second level cache being modular with a plurality of interleaved modules;
one or more memory controllers capable of operatively communicating with the two-level cache hierarchy and with an off-chip memory;
a cache coherence protocol;
one or more coherence protocol engines;
an intra-chip switch; and
an interconnect subsystem. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
-
-
30. A method for scalable chip-multiprocessing, comprising:
-
providing on a single chip a plurality of processor cores, a two-level cache hierarchy including a pair of instruction and data caches for, and private to, each processor core, the pair being first level caches, and a second level cache with a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores, the second level cache being modular with a plurality of interleaved modules, one or more memory controllers capable of operatively communicating with the two-level cache hierarchy and with an off-chip memory, a cache coherence protocol, one or more coherence protocol engines, an intra-chip switch, and an interconnect subsystem, wherein the single chip creates a node; and
providing one or more than one of the nodes to create, in a modular scalable fashion, a glueless multiprocessor. - View Dependent Claims (31)
-
Specification