P-N junction-based structures utilizing HVPE grown III-V compound layers

• US 20020047135A1
• Filed: 05/17/2001
• Published: 04/25/2002
• Est. Priority Date: 11/18/1997
• Status: Abandoned Application

• Current Assignee: Technologies And Devices International Inc.
• Original Assignee: Technologies And Devices International Inc.
• Inventors: Melnik, Yuri V., Dmitriev, Vladimir A., Vassilevski, Konstantin V., Nikolaev, Audrey E.
• Application Number:
  US09/861,022
• Publication Number:
  US 20020047135A1
• Time in Patent Office: Days
• US Class Current: 257/189
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/40 AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02543 Phosphides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0259 Microstructure
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 31/0304 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials

Abstract

A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis. The quantum dot layer is preferably comprised of Al_xB_yIn_zGa_1-x-y-zN, InGaN_1-a-bP_aAs_b, or Al_xB_yIn_zGa_1-x-y-zN_1-a-bP_aAs_b.

Claims

1. A III-V p-n junction device, comprising:

a substrate;

a high temperature n-type III-V compound layer grown directly on said substrate, wherein said high temperature n-type III-v compound layer is grown at a temperature greater than 900°

C. using HVPE techniques, wherein a low temperature buffer layer is not interposed between said substrate and said high temperature n-type III-V compound layer; and

a p-type III-V compound layer grown directly on said high temperature n-type III-V compound layer using HVPE techniques, said p-type III-V compound layer forming a p-n junction with said high temperature n-type III-V compound layer.

2. The III-V p-n junction device of claim 1, wherein said high temperature n-type III-V compound layer is grown at a temperature greater than 950°

C. using HVPE techniques.

3. The III-V p-n junction device of claim 1, wherein said high temperature n-type III-V compound layer is grown at a temperature greater than 1000°

C. using HVPE techniques.

4. The III-V p-n junction device of claim 1, further comprising:

a first contact deposited on said p-type III-V compound layer; and

a second contact deposited on said substrate.

5. The III-V p-n junction device of claim 4, wherein said first and second contacts are selected from the group of materials consisting of nickel, palladium, gold, platinum, gold-nickel, and palladium-platinum.

6. The III-V p-n junction device of claim 1, further comprising:

a first contact deposited on said p-type III-V compound layer; and

a second contact deposited on a surface of said high temperature n-type III-V compound layer.

7. The III-V p-n junction device of claim 6, wherein said surface is an etched surface of said high temperature n-type III-V compound layer.

8. The III-V p-n junction device of claim 6, wherein said first and second contacts are selected from the group of materials consisting of nickel, palladium, gold, platinum, gold-nickel, and palladium-platinum.

9. The III-V p-n junction device of claim 1, wherein said p-n junction is a homojunction.

10. The III-V p-n junction device of claim 1, wherein said p-n junction is a heterojunction.

11. The III-V p-n junction device of claim 1, wherein said high temperature n-type III-V compound layer is selected from the group of materials consisting of GaN and AlGaN.

12. The III-V p-n junction device of claim 1, wherein said p-type III-V compound layer is selected from the group of materials consisting of GaN and AlGaN.

13. The III-V p-n junction device of claim 1, wherein said substrate is selected from the group of materials consisting of sapphire, silicon carbide, gallium nitride, and silicon.

14. The III-V p-n junction device of claim 1, wherein said p-type III-V compound layer includes at least one acceptor impurity metal selected from the group of metals consisting of Mg, Zn, and MgZn.

15. The III-V p-n junction device of claim 14, wherein a concentration of said at least one acceptor impurity metal within said p-type III-V compound layer is in the range of 10¹⁸ to 10²¹ atoms cm³.

16. The III-V p-n junction device of claim 14, wherein a concentration of said at least one acceptor impurity metal within said p-type III-V compound layer is in the range of 10¹⁹ to 10²⁰ atoms cm³.

17. The III-V p-n junction device of claim 14, wherein said p-type III-V compound layer is co-doped with O.

18. The III-V p-n junction device of claim 1, wherein said high temperature n-type III-V compound layer includes at least one donor impurity selected from the group of materials consisting of O, Si, Ge, and Sn.