P-N junction-based structures utilizing HVPE grown III-V compound layers
First Claim
1. A III-V p-n junction device, comprising:
- a substrate;
a high temperature n-type III-V compound layer grown directly on said substrate, wherein said high temperature n-type III-v compound layer is grown at a temperature greater than 900°
C. using HVPE techniques, wherein a low temperature buffer layer is not interposed between said substrate and said high temperature n-type III-V compound layer; and
a p-type III-V compound layer grown directly on said high temperature n-type III-V compound layer using HVPE techniques, said p-type III-V compound layer forming a p-n junction with said high temperature n-type III-V compound layer.
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Abstract
A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis. The quantum dot layer is preferably comprised of AlxByInzGa1-x-y-zN, InGaN1-a-bPaAsb, or AlxByInzGa1-x-y-zN1-a-bPaAsb.
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Citations
18 Claims
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1. A III-V p-n junction device, comprising:
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a substrate;
a high temperature n-type III-V compound layer grown directly on said substrate, wherein said high temperature n-type III-v compound layer is grown at a temperature greater than 900°
C. using HVPE techniques, wherein a low temperature buffer layer is not interposed between said substrate and said high temperature n-type III-V compound layer; and
a p-type III-V compound layer grown directly on said high temperature n-type III-V compound layer using HVPE techniques, said p-type III-V compound layer forming a p-n junction with said high temperature n-type III-V compound layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification