Voltage level detection circuit and voltage level detection method

• US 20020047729A1
• Filed: 10/18/2001
• Published: 04/25/2002
• Est. Priority Date: 10/23/2000
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Sugimoto, Hirokazu, Hirata, Takashi, Takahashi, Satoshi, Terada, Yutaka, Komatsu, Yoshihide, Akamatsu, Hironori
• Granted Patent: US 6,417,700 B1
• Time in Patent Office: Days
• US Class Current: 327/50
• CPC Class Codes: H03M 1/0626 by filtering
• CPC Class Codes: H03M 1/0872 by disabling changes in the output during the transitions, e.g. by holding or latching
• CPC Class Codes: H03M 1/145 the steps being performed sequentially in series-connected stages H03M1/141, H03M1/143, H03M1/16 take precedence
• CPC Class Codes: H03M 1/34 Analogue value compared with reference values H03M1/48 takes precedence
• CPC Class Codes: H03M 1/36 simultaneously only, i.e. parallel type

Abstract

In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.

Claims

1. A circuit for detecting the voltage level of an analog signal comprising:

a conversion circuit for comparing the voltage level of the analog signal with a plurality of different reference potentials and converting the analog signal to a plurality of digital signals based on the comparison result; and

a filter circuit for filtering the plurality of digital signals output from the conversion circuit,

wherein the filter circuit matches timings of at least one of rising edges and falling edges of at least two of the plurality of digital signals with each other.

2. The circuit of claim 1, wherein the filter circuit includes a RS flipflop for receiving an inverted signal of a first digital signal among the plurality of digital signals as reset input and a second digital signal among the plurality of digital signals as set input.

3. A circuit for detecting the voltage level of an analog signal comprising:

a conversion circuit for comparing the voltage level of the analog signal with a plurality of reference potentials including at least a first reference potential and a second reference potential lower than the first reference potential, and converting the analog signal to a plurality of digital signals based on the comparison result,

wherein the conversion circuit comprises;

a first comparator for comparing the voltage level of the analog signal with the first reference potential;

a selector for selecting and outputting one of the first and second reference potentials; and

a second comparator for comparing the voltage level of the analog signal with the reference potential selected and output from the selector, and

wherein the selector receives an output of the second comparator as a selection signal, and selects and outputs the first reference potential when the selection signal indicates that the voltage level of the analog signal is lower than the reference potential, and selects and outputs the second reference potential when the selection signal indicates that the voltage level of the analog signal is higher than the reference potential.

4. A circuit for detecting the voltage level of an analog signal comprising:

a conversion circuit for comparing the voltage level of the analog signal with a first reference potential and a second reference potential, and converting the analog signal to first and second digital signals based on the comparison result; and

a sample-hold circuit for receiving the first and second digital signals and outputting first and second hold signals representing the voltage level of the analog signal,

wherein, in a case where the logical level of the first digital signal changes, the sample-hold circuit holds the first hold signal at one logical level when the logical level of the second digital signal does not change, and holds the second hold signal at the one logical level when the logical level of the second digital signal changes.

5. A method for detecting the voltage level of an analog signal, comprising the steps of:

(a) comparing the voltage level of the analog signal with a plurality of different reference potentials;

(b) converting the analog signal to a plurality of digital signals based on the comparison result in step (a); and

(c) matching timings of at least one of rising edges and falling edges of at least two of the plurality of digital signals with each other.