Method and device for identifying a data packet in a data stream

• US 20020048330A1
• Filed: 10/19/2001
• Published: 04/25/2002
• Est. Priority Date: 10/19/2000
• Status: Active Grant

• Current Assignee: Crystal Mountain Communications, LLC (Ascend Innovation Management, LLC)
• Original Assignee: Nokia Corporation
• Inventors: Kafemann, Harald, Schetelig, Markus
• Granted Patent: US 7,158,598 B2
• Time in Patent Office: Days
• US Class Current: 375/340
• CPC Class Codes: H04L 25/062 Setting decision thresholds using feedforward techniques only
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15
• CPC Class Codes: H04W 24/00 Supervisory, monitoring or testing arrangements

Abstract

The invention relates to a method and a device for identifying a data packet in a data stream, in which by means of a d.c. voltage quota determining circuit (30) the d.c. voltage quota (dc) for a demodulated digital input signal (S_in) is calculated, in which a k-bit word is allocated to the input signal (S_in), in that for each symbol of the input signal (S_in) corresponding to a bit a bit value (1 or 0) is determined by a decoding circuit (37) as a function of the d.c. voltage quota (dc), in which the k-bit word corresponding to the input signal (S_in) is compared by a comparison and correlation calculating circuit (41) with an expected k-bit synchronisation word in order to determine a correlation value (c_v) and in which a packet identification signal (P_d) is generated by a correlation value comparison circuit (43) if the correlation value (c_v) is greater than a correlation threshold value (c_th). Calculation of the d.c. voltage quota (dc) is therein repeated continually at least until a packet identification signal (P_d) indicates that a data packet is being received.

Claims

1. Method for identifying a data packet in a data stream in which

the d.c. voltage quota (dc) for a demodulated digital input signal (S_in) is calculated,

a k-bit word is allocated to the input signal (S_in), in that for each symbol of the input signal (S_in) corresponding to a bit a bit value (1 or 0) is determined as a function of the d.c. voltage quota (dc),

the k-bit word corresponding to the input signal(S_in) is compared with an expected k-bit synchronisation word in order to determine a correlation value (c_v) and

a packet identification signal (P_d) is generated if the correlation value (c_v) is greater than a correlation threshold value (c_th).

2. Method according to claim 1, characterised in that for calculating the d.c. voltage quota (dc)

the input signal (S_in) is scanned in order to generate a sequence of scanned values (h_i) corresponding to the input signal (S_in) and

from a selected number (1) of scanned values (h_i) the d.c. voltage quota (dc) of the input signal (S_in) is calculated.

3. Method according to claim 2, characterised in that the d.c. voltage quota (dc) of the input signal (S_in) is calculated again after each scan of the input signal (S_in) at least until the correlation value (c_v) determined by comparison of the k-bit word corresponding to the input signal (S_in) with an expected k-bit synchronisation word is greater than the correlation threshold value (c_th).

4. Method according to claim 2 or 3, characterised in that

after a packet identification signal (P_d) has been generated the corresponding correlation value (c_v) is stored and scanning of the input signal (S_in), calculation of the d.c. voltage quota (dc) and comparison of the k-bit word corresponding to the input signal (S_in) with an expected k-bit synchronisation word to determine the correlation value (c_v) is still continued for a predeterminable period of time and

a new packet identification signal (P_d) is generated if a newly determined correlation value (c_v) is greater than the correlation threshold value (c_th) and greater than the previously determined stored correlation value (c_v).

5. Method according to one of the preceding claims, characterised in that to determine the k-bit word corresponding to the input signal (S_in)

the input signal (S_in) is scanned in order to generate a sequence of scanned values (h_i) corresponding to the input signal (S_in) and

a bit value (1 or 0) is allocated to each scanned value (h_i) of a selected multiplicity (k) of scanned values (h_i) as a function of the d.c. voltage quota (dc) of the input signal (S_in).

6. Method according to one of claims 1 to 5, characterised in that

the input signal (S_in) is scanned at a frequency (f_sample) which is chosen in such a way that the over-scanning rate (S_r) is at least equal to two (S_r≧

2), that therefore at least two scanned values (h_i) are determined for each symbol and

to form the k-bit word corresponding to the input signal (S_in) in each case only one scanned value (h_i) per symbol is selected.

7. Method according to claim 6, characterised in that the multiplicity (k) of scanned values (h_i) for forming the k-bit word corresponding to the input signal (S_in) is selected from the sequence of scanned values (h_i) in such a way that the selected scanned values (h_i) within the sequence in each case are substantially the same distance apart.

8. Method according to one of the preceding claims, characterised in that

the number (1) of scanned values (h_i) for calculating the d.c. voltage quota (dc) of the input signal (S_in) is chosen in such a way that the scanned values (h_i) correspond to areas in the expected k bit synchronisation word which substantially have the same number of bits with the value “

0” and

bits with the value “

1” and

the d.c. voltage quota (dc) is calculated as an average value of the scanned values (h_i).

9. Method according to claim 8, characterised in that the number (1) of scanned values (h₁) for calculating the d.c. voltage quota (dc) consists of at least one group of scanned values (h_i) in direct succession to one another, which correspond to several successive symbols.

10. Method according to claim 8 or 9, characterised in that the number (1) of scanned values (h_i) for calculating the d.c. voltage quota (dc) consists of two groups of scanned values (h_i), which are separated from one another by a multiplicity of scanned values (h_i).

16. Device according to one of the preceding claims, characterised in that the comparison and correlation calculating circuit (41) connected to the decoding circuit (37) and a register (42) storing the expected k-bit synchronisation word, besides a multiplicity (k) of comparison circuits for comparing the k-bit word supplied by the decoding circuit (37) and corresponding to the input signal with the k-bit synchronisation word, has a correlation element which adds a one for each coinciding bit pair in order to calculate the correlation value (c_v).

11. Device for identifying data packets in a data receiving stream with

a delay line (22) which has a number (n) of storage places (22.i), in which scanned values (h_i) of a demodulated digital input signal (S_in) are stored in series,

a d.c. voltage quota determining circuit (30), which is connected to the delay line (22) in order to calculate a d.c. voltage quota (dc) of the input signal (S_in) as an average value of a selected number (1) of scanned values (h_i),

a decoding circuit (37) connected to the delay line (22) and the d.c. voltage quota determining circuit (30), which compares a multiplicity (k) of scanned values (h_i) with the d.c. voltage quota (dc) in order to allocate a bit value (0 or 1) to each scanned value (h_i) and in this way to form a k-bit word corresponding to the input signal (S_in)

a comparison and correlation calculating circuit (41) which compares the k-bit word corresponding to the input signal (S_in) with an expected k-bit synchronisation word and calculates a correlation value (c_v) for the k-bit word corresponding to the input signal (S_in) and

a correlation value comparison circuit (43) which compares the correlation value (c_v) supplied by the comparison and correlation calculating circuit (41) with a correlation threshold value (c_th) in order to supply a packet identification signal (P_d) if the correlation value (c_v) is greater than or equal to the correlation threshold value (c_th).

12. Device according to claim 11, characterised in that the number (n) of storage places (22.i) of the delay line (22) corresponds to the number (k) of bits in the k-bit synchronisation word multiplied by the over-scanning rate (S_r), in other words with the number of scanned values (h_i) per symbol.

13. Device according to claim 11 or 12, characterised in that the decoding circuit (37) comprises a multiplicity (k) of comparison circuits, to which in each case is applied the d.c. voltage quota (dc) and each of which is connected to one of the storage places (22.i) of the delay line (22) in order to compare the respective scanned value (h_i) with the d.c. voltage quota (dc) and to determine a bit value (1 or 0), so the k-bit word corresponding to the input signal (S_in) is applied to outputs (out(i)) of the decoding circuit.

14. Device according to claim 11, 12 or 13, characterised in that the d.c. voltage quota determining circuit (30) has at least one addition circuit (33) and one division circuit (36) connected to the output of the addition circuit (33) via a holding element (34), wherein

one input of the addition circuit (33) is connected to a first storage place (22.m₁, 22.m₃) of the delay line (22) and another input is connected to a second storage place (22.m₂, 22.m₄) of the delay line (22), which is separated from the first storage place (22.m₁, 22.m₃) by a multiplicity of storage places (22.i),

the input which is connected to the second storage place (22.m₂, 22.m₄) is negated and

the output of the addition circuit (33) is fed back to a third input via the holding element (34), so that with each addition the result of the preceding addition is added on and wherein

the sum supplied by the holding circuit (34) is divided in the division circuit by a value (m₁−

m₂;

m₃−

m₄) corresponding to the distance between the storage places (22.m₁, 22.m₃;

22.m₂, 22.m₄) in order to calculate the d.c. voltage quota (dc).

15. Device according to claim 14, characterised in that two addition circuits (33) connected to storage places (22.m₁, 22.m₃;

22.m₂, 22.m₄) of the delay line (22) are provided, the output signals of which are supplied to the division circuit (36) via a further addition circuit (35).