Process for integrating dielectric optical coatings into micro-electromechanical devices

• US 20020048839A1
• Filed: 09/18/2001
• Published: 04/25/2002
• Est. Priority Date: 10/19/2000
• Status: Active Grant

• Current Assignee: Axsun Technologies Incorporated
• Original Assignee: Axsun Technologies Incorporated
• Inventors: Cook, Christopher C., Flanders, Dale C., Miller, Michael F., Nagle, Steven F., Le, Minh Van
• Granted Patent: US 6,790,698 B2
• Time in Patent Office: Days
• US Class Current: 438/50
• CPC Class Codes: B81B 2201/042 Micromirrors, not used as optical switches
• CPC Class Codes: B81B 2201/047 Optical MEMS not provided for in B81B2201/042 - B81B2201/045
• CPC Class Codes: B81B 3/0083 Optical properties
• CPC Class Codes: B81C 1/0038 Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
• CPC Class Codes: B81C 2201/0159 Lithographic techniques not provided for in B81C2201/0157
• CPC Class Codes: B81C 2201/053 Depositing a protective layers
• CPC Class Codes: B81C 2201/056 Releasing structures at the end of the manufacturing process
• CPC Class Codes: G02B 26/001 based on interference in an adjustable optical cavity interference filters G02B5/28; devices or arrangements using multiple reflections in spectrometry or monochromators G01J3/26

Abstract

A process for patterning dielectric layers of the type typically found in optical coatings in the context of MEMS manufacturing is disclosed. A dielectric coating is deposited over a device layer, which has or will be released, and patterned using a mask layer. In one example, the coating is etched using the mask layer as a protection layer. In another example, a lift-off process is shown. The primary advantage of photolithographic patterning of the dielectric layers in optical MEMS devices is that higher levels of consistency can be achieved in fabrication, such as size, location, and residual material stress. Competing techniques such as shadow masking yield lower quality features and are difficult to align. Further, the minimum feature size that can be obtained with shadow masks is limited to ˜100 μm, depending on the coating system geometry, and they require hard contact with the surface of the wafer, which can lead to damage and/or particulate contamination.

Claims

1. A process for fabricating a deflectable optical MEMS structure having a dielectric coating, the process comprising:

forming a device layer;

depositing a dielectric optical coating over the device layer;

depositing a mask layer over the device layer;

patterning the mask layer;

transferring a pattern of the mask layer into the dielectric coating; and

removing at least part of a sacrificial layer to release the device layer.

2. A process as claimed in claim 1, wherein the step of removing the sacrificial layer is performed after the patterning of the dielectric coating.

3. A process as claimed in claim 1, wherein the step of removing the sacrificial layer is performed, at least in part, before the patterning of the dielectric coating.

4. A process as claimed in claim 1, wherein the step of forming the device layer comprises depositing the device layer on the sacrificial layer.

5. A process as claimed in claim 1, wherein the step of forming the device layer comprises bonding the device layer to the sacrificial layer.

6. A process as claimed in claim 1, wherein the step of depositing the mask layer comprises depositing a photoresist material.

7. A process as claimed in claim 1, wherein the step of depositing the mask layer comprises depositing a metal layer.

8. A process as claimed in claim 1, wherein the step of patterning the mask layer comprises removing a portion mask layer in the optical port region.

9. A process as claimed in claim 1, wherein the step of patterning the mask layer comprises removing portions of the mask layer outside of the optical port region.

10. A process as claimed in claim 1, wherein the step of transferring the pattern of the mask layer into the dielectric coating comprises removing the mask layer and portions of the dielectric coating on the mask layer.

11. A process as claimed in claim 1, wherein the step of transferring the pattern of the mask layer into the dielectric coating comprises etching portions of the dielectric coating exposed by the mask layer.

12. A process as claimed in claim 1, further comprising patterning tethers into the device layer.

13. A process as claimed in claim 1, wherein the step of removing at least part of the sacrificial layer is performed after the step of depositing the dielectric optical coating;

the process further comprising covering the dielectric optical coating with a protecting layer during removal of the sacrificial layer.

14. A process as claimed in claim 1, further comprising installing the membrane at one end of a laser cavity.

15. A process as claimed in claim 1, further comprising installing the membrane opposite a stationary reflector to form a tunable Fabry-Perot filter.