Method and apparatus for reducing leakage power in a cache memory
First Claim
1. A cache memory, comprising:
- a plurality of cache lines for storing a value from main memory; and
a timer associated with each of said plurality of cache lines, each of said timers configured to control a signal that removes power to said associated cache line after a decay interval.
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Accused Products
Abstract
A method and apparatus are disclosed for reducing leakage power in a cache memory. A cache decay technique is employed for both data and instruction caches that removes power from cache lines that have not been accessed for a predefined time interval, referred to as the decay interval. The cache-line granularity of the present invention permits a significant reduction in leakage power while at the same time preserving much of the performance of the cache. The decay interval is maintained using a timer that is reset each time the corresponding cache line is accessed. The decay interval may be fixed or variable. Once the decay interval timer exceeds a specified decay interval, power to the cache line is removed. Once power to the cache line is removed, the contents of the data and tag fields are allowed to decay and the valid bit associated with the cache line is reset. When a cache line is later accessed after being powered down by the present invention, a cache miss is incurred while the cache line is again powered up and the data is obtained from the next level of the memory hierarchy.
45 Citations
35 Claims
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1. A cache memory, comprising:
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a plurality of cache lines for storing a value from main memory; and
a timer associated with each of said plurality of cache lines, each of said timers configured to control a signal that removes power to said associated cache line after a decay interval. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method for reducing leakage power in a cache memory, said cache memory having a plurality of cache lines, said method comprising the steps of:
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providing a timer for each of said cache lines;
resetting said timer each time said cache line is accessed; and
removing power from said associated cache line after a decay interval. - View Dependent Claims (21, 22, 23, 24, 25, 26, 28, 29, 30, 31, 32, 33, 35)
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27. A cache memory, comprising:
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a plurality of cache lines for storing a value from main memory, each of said cache lines comprised of one or more dynamic random access memory (DRAM) cells, each of said DRAM cells being refreshed each time said cache line is accessed, each of said DRAM cells reliably storing said value for a safe period; and
a timer associated with each of said plurality of cache lines, each of said timers controlling a signal that resets a valid bit associated with said cache line after said safe period.
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34. A method for reducing leakage power in a cache memory, said cache memory having a plurality of cache lines, for storing a value from main memory, each of said cache lines comprised of one or more dynamic random access memory (DRAM) cells, each of said DRAM cells reliably storing said value for a safe period, said method comprising the steps of:
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refreshing each of said DRAM cells each time said corresponding cache line is accessed,; and
providing a timer for each of said cache lines;
resetting said timer each time said cache line is accessed; and
resetting a valid bit associated with said cache line after said safe period.
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Specification