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Method of designing semiconductor integrated circuit device, and apparatus for designing the same

  • US 20020049957A1
  • Filed: 03/07/2001
  • Published: 04/25/2002
  • Est. Priority Date: 10/05/2000
  • Status: Active Grant
First Claim
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1. A method of designing a semiconductor integrated circuit device, which lays out and wires a circuit cell group according to net information, comprising:

  • a longest wiring load calculating step for calculating a wiring load of a drivable allowable longest wiring having taken into consideration a waveform rounding, as a first load for each load capacitance driven by the circuit cell;

    a wiring load estimating step for calculating an input load capacitance of a next-stage circuit cell and a second load estimated as a wiring load from the circuit cell to the next-stage circuit cell; and

    a determining step for comparing the first load related to the load capacitance corresponding to the input load capacitance, and the second load in size, and judging a signal waveform inputted to the next-stage circuit cell to be less than or equal to a predetermined waveform rounding limit value and drivable when the second load is smaller than the first load.

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