Method of designing semiconductor integrated circuit device, and apparatus for designing the same

• US 20020049957A1
• Filed: 03/07/2001
• Published: 04/25/2002
• Est. Priority Date: 10/05/2000
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yoneda, Takashi, Hosono, Toshikatsu, Fujita, Miyako, Wakita, Makoto
• Granted Patent: US 6,550,050 B2
• Time in Patent Office: Days
• US Class Current: 716/5
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

In a method of and an apparatus for designing a semiconductor integrated circuit device, which are capable of causing each waveform rounding to fall within a predetermined limit value without delay calculations at an early stage of the development of the semiconductor integrated circuit device, a wiring path resistance Rpath from an output terminal of a target circuit cell to a next-stage circuit cell and an allowable longest wiring resistance RtL drivable by the target circuit cell are compared. When Rpath is less than or equal to RtL (S4: YES), the sum Rtotal of resistances of wiring loads in a net and RtL are compared. If Rtotal is less than or equal to RtL (S5: YES), then the next-stage circuit cell is judged to be drivable within a predetermined waveform rounding limit value. When Rtotal is greater than RtL (S5: NO), an effective resistance Rw of each wiring load and an allowable longest wiring effective resistance RwL are compared. When Rw is less than or equal to RwL (S6: YES), the waveform rounding at the next-stage circuit cell is judged to fall within a predetermined limit value.

Claims

1. A method of designing a semiconductor integrated circuit device, which lays out and wires a circuit cell group according to net information, comprising:

a longest wiring load calculating step for calculating a wiring load of a drivable allowable longest wiring having taken into consideration a waveform rounding, as a first load for each load capacitance driven by the circuit cell;

a wiring load estimating step for calculating an input load capacitance of a next-stage circuit cell and a second load estimated as a wiring load from the circuit cell to the next-stage circuit cell; and

a determining step for comparing the first load related to the load capacitance corresponding to the input load capacitance, and the second load in size, and judging a signal waveform inputted to the next-stage circuit cell to be less than or equal to a predetermined waveform rounding limit value and drivable when the second load is smaller than the first load.

2. The method according to claim 1, wherein the first load includes a first resistance corresponding to the resistance of the allowable longest wiring,

the second load includes a second resistance corresponding to the resistance of a wiring path for connecting the circuit cell and the next-stage circuit cell, and a third resistance corresponding to the sum of resistances of all wiring loads driven by the circuit cell, and

the determining step compares the first resistance and the second resistance or the third resistance, and judges the signal waveform to be less than or equal to the predetermined waveform rounding limit value when the second resistance or the third resistance is smaller than the first resistance.

3. The method according to claim 1, wherein the longest wiring load calculating step includes the calculation of a first wiring load parameter upon conversion to a first wiring load model based on the first load and the load capacitance,

the wiring load estimating step includes the calculation of a second wiring load parameter upon conversion to a second wiring load model based on the second load and the input load capacitance connected to the second load, and

the determining step compares the first wiring load parameter and the second wiring load parameter and judges the signal waveform to be less than or equal to the predetermined waveform rounding limit value when the second wiring load parameter is smaller than the first wiring load parameter.

4. The method according to claim 3, wherein the first load includes a first resistance corresponding to the resistance of the allowable longest wiring and a first capacitance corresponding to a load capacitance on the allowable longest wiring,

the first wiring load model is a π

-type wiring load model converted to a wiring load model based on the first resistance, the first capacitance and the load capacitance,

the first wiring load parameter is a fourth resistance modeled by the first wiring load model,

the second load includes a second resistance corresponding to resistances of all wiring paths for connecting the circuit cell and the next-stage circuit cells and a second capacitance corresponding to load capacitances on all the wiring paths,

the second wiring load model is a wiring load model obtained by converting a wiring having branches to a a-type wiring load model by a predetermined approximation method, and

the second wiring load parameter is a fifth resistance modeled by the second wiring load model.

5. The method according to claim 1, wherein the first load includes a first resistance corresponding to the resistance of the allowable longest wiring,

the second load includes a second resistance corresponding to the resistance of a wiring path for connecting the circuit cell and the next-stage circuit cell, and a third resistance corresponding to the sum of resistances of all the wiring loads driven by the circuit cell,

the determining step compares the first resistance and the second resistance or the third resistance, and judges the signal waveform to be greater than or equal to the predetermined waveform rounding limit value when the second resistance or the third resistance is larger than the first resistance,

the longest wiring load calculating step includes the calculation of a first wiring load parameter upon conversion to a first wiring load model based on the first load and the load capacitance,

the wiring load estimating step includes the calculation of a second wiring load parameter upon conversion to a second wiring load model based on the second load and the input load capacitance connected to the second load, and

the determining step compares the first wiring load parameter and the second wiring load parameter and judges the signal waveform to be less than or equal to the predetermined waveform rounding limit value when the second wiring load parameter is smaller than the first wiring load parameter.

6. The method according to claim 5, wherein the first load includes a first resistance corresponding to the resistance of the allowable longest wiring and a first capacitance corresponding to a load capacitance on the allowable longest wiring,

the first wiring load model is a π

-type wiring load model converted to a wiring load model based on the first resistance, the first capacitance and the load capacitance,

the first wiring load parameter is a fourth resistance modeled by the first wiring load model,

the second load includes a second resistance corresponding to resistances of all wiring paths for connecting the circuit cell and the next-stage circuit cells and a second capacitance corresponding to load capacitances on all the wiring paths,

the second wiring load model is a wiring load model obtained by converting a wiring having branches to a π

-type wiring load model by a predetermined approximation method, and

the second wiring load parameter is a fifth resistance modeled by the second wiring load model.

7. The method according to claim 1, wherein the longest wiring load calculating step comprises an individual longest load calculating step for calculating, as a third load, a wiring load at the time that a waveform rounding of a signal waveform driven by each output terminal under each individual input terminal condition of the circuit cell reach the predetermined waveform rounding limit value, every load capacitance with respect to the each output terminal, and

a selecting step for selecting the minimum value among the third loads calculated under the respective input terminal conditions, every load capacitance with respect to the each output terminal, and setting the same as the first load corresponding to the each load capacitance at each of the output terminals.

8. The method according to claim 1, wherein the longest wiring load calculating step calculates a wiring load at the time that a waveform rounding of a signal waveform reach the predetermined waveform rounding limit value, as a first load corresponding to the respective load capacitance at the output terminal according to an input terminal condition under which drive capacities are minimized every output terminal of the circuit cell.

9. The method according to claim 7, wherein the waveform rounding of a signal inputted to the circuit cell is set to a predetermined time.

10. The method according to claim 8, wherein the waveform rounding of a signal inputted to the circuit cell is set to a predetermined time.

13. A recording medium having programs recorded therein for implementing the method of designing the semiconductor integrated circuit device as described in claim 1.

11. An apparatus for designing a semiconductor integrated circuit device, which lays out and wires a circuit cell group according to net information, comprising:

longest wiring load calculating unit for calculating a wiring load of a drivable allowable longest wiring having taken into consideration a waveform rounding, as a first load for each load capacitance driven by the circuit cell;

wiring load estimating unit for calculating an input load capacitance of a next-stage circuit cell and a second load estimated as a wiring load from the circuit cell to the next-stage circuit cell; and

determining unit for comparing the first load related to the load capacitance corresponding to the input load capacitance, and the second load in size, and judging a signal waveform inputted to the next-stage circuit cell to be less than or equal to a predetermined waveform rounding limit value and drivable when the second load is smaller than the first load.

12. The apparatus according to claim 11, wherein the longest wiring load calculating unit comprises individual longest load calculating unit for calculating, as a third load, a wiring load at the time that a waveform rounding of a signal waveform driven by each output terminal under each individual input terminal condition of the circuit cell reach the predetermined waveform rounding limit value, every load capacitance with respect to the respective output terminal, and

selecting unit for selecting the minimum value among the third loads calculated under the respective input terminal conditions, every load capacitance with respect to the respective output terminal, and setting the same as the first load corresponding to each load capacitance at each of the output terminals.