Integrated EMI shield utilizing a hybrid edge

• US 20020050401A1
• Filed: 08/10/2001
• Published: 05/02/2002
• Est. Priority Date: 08/20/1999
• Status: Active Grant

• Current Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Original Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Inventors: Youker, Nick A., Hansen, John E., Blood, James E.
• Granted Patent: US 6,865,804 B2
• Time in Patent Office: Days
• US Class Current: 174/255
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15156 Side view
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H05K 9/0039 Galvanic coupling of ground layer on printed circuit board [PCB] to conductive casing printed shielding conductors, ground planes or power planes for reduction of cross-talk or noise in printed circuits H05K1/0218
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

The present embodiments and associated methods provide for an integrated EMI shield for effective shielding not only from emissions perpendicular to the integrated circuit (IC) chip carrier but also parallel (edgewise) to the carrier. In one embodiment, an IC chip carrier comprises an insulating ceramic substrate and at least one internal electrically conductive layer being a circuit ground, portions of which extend to the edge of the substrate, the internal electrically conductive layer in electrical contact with an electrically conductive layer applied to a portion of the substrate edge. This provides a horizontal hybrid ground plane which can be used as an EMI shield that runs horizontally to the chip as well as a hybrid edge EMI shield perpendicular along at least a portion of the edge. This edge shield protects internal circuitry from exterior EMI emissions directed towards the chip carrier edge portion incorporating the shield.

Claims

1. An integrated circuit chip carrier, comprising:

an electrically insulating substrate having an edge;

at least one internal electrically conductive layer connected to circuit ground, at least a portion of the conductive layer extending to the edge of the substrate; and

a second electrically conductive layer applied to at least a portion of the substrate edge, the internal electrically conductive layer in electrical contact with the second electrically conductive layer.

2. An integrated circuit chip carrier according to claim 1, wherein the substrate is a ceramic material.

3. An integrated circuit chip carrier according to claim 2, wherein the second electrically conductive layer is tungsten.

4. An integrated circuit chip carrier according to claim 2, wherein the second electrically conductive layer is molybdenum.

5. A method for providing electromagnetic interference edge shielding to an integrated circuit chip carrier, the chip carrier including top and bottom surfaces and an edge, and at least one internal electric ground layer, the steps comprising:

exposing at least a portion of the internal ground layer along at least a portion of the substrate edge; and

applying an electrically conductive layer to at least a portion of the substrate edge, the conductive layer being applied over the exposed portion of the ground layer and in electrical contact with said ground layer.

6. A method for providing an integrated circuit chip carrier with electromagnetic interference edge shielding, the steps comprising:

stacking-up a plurality of ceramic green sheets, at least one green sheet having an applied electrically conductive first layer being a circuit ground;

applying heat and pressure to the stack-up to sinter the green sheets into a monolithic structure and to metalize the first conductive layer;

exposing at least a portion of the first conductive layer on the structure edge;

applying a second electrically conductive layer of metalized paste to at least a portion of the structure edge and in electrical contact with the first conductive layer; and

sintering the structure a second time to metalize the paste and to create a consolidated chip carrier.

7. A method for providing an integrated circuit chip carrier with electromagnetic interference edge shielding, according to claim 6, including the step of applying the second conductive layer using a printing process.

8. A method for providing an integrated circuit chip carrier with electromagnetic interference edge shielding, according to claim 6, including the step of applying the second conductive layer using a plating process.

9. A method for providing an integrated circuit chip carrier with electromagnetic interference edge shielding, according to claim 6, including the step of applying the second conductive layer to the entire edge of the substrate.

10. A circuit board comprising:

a substrate having a top surface and a bottom surface, the substrate comprising a thermoplastic polymeric material;

electrical circuitry disposed on the top and bottom surfaces of the substrate;

an electrically grounded planar conductive layer substantially encapsulated by the substrate, the planar conductive layer shielding the electrical circuitry from electromagnetic interference originating on a side of the sheet opposite from the electrical circuitry;

a least a portion of the planar conductive layer extending outward to the edge of the substrate; and

a conductive layer applied on at least a portion of the edge of the substrate, wherein the edge conductive layer is electrically connected to the planar conductive layer, whereby the edge conductive layer and the planar conductive layer are designed to electrically block external EMI emissions.

11. A shielded electric circuit board, comprising:

a planar substrate having a top and bottom surface and an edge;

at least one conductive ground layer internal to the substrate, at least a portion of the ground layer exposed on the substrate edge; and

conductive layer applied to at least a portion of the substrate edge, the conductive layer electrically connected to the ground layer exposed portions.

12. The shielded electric circuit board in accordance with claim 11, wherein the substrate includes at least one internal signal layer, said signal layer being co-planar with the internal ground layer and being electrically insulated from the ground layer and the external surfaces of said substrate.