BURN-IN TEST METHOD FOR A SEMICONDUCTOR CHIP AND BURN-IN TEST APPARATUS THEREFOR

• US 20020050813A1
• Filed: 05/11/1999
• Published: 05/02/2002
• Est. Priority Date: 12/07/1998
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: YAMAMOTO, SHIGEHISA
• Granted Patent: US 6,404,219 B1
• Time in Patent Office: Days
• US Class Current: 324/158.1
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads

Abstract

A burn-in test method and apparatus and a semiconductor chip to be used in a burn-in test method that allow current stress to be imposed on every circuit node by varying a power supply voltage in pulse form, and thereby enables an efficient burn-in test. A burn-in test is performed efficiently by imposing current stress to every internal circuit by supplying the internal circuits of a semiconductor chip with a pulse Vcc voltage that varies from 0 V to a burn-in voltage Vbi. The burn-in test time can further be shortened by varying the Vcc voltage in pulse form in a range from a voltage that is higher than or equal to the threshold voltage Vth to the burn-in voltage Vbi or by setting the pulse waveform of the Vcc voltage in such a manner that a high-voltage period T_H is longer than a low-voltage period T_L.

Claims

1. A burn-in test method for a semiconductor chip, comprising:

a pulse voltage supplying step of supplying an inverter circuit in a semiconductor chip with a pulse voltage that is output from a pulsed power supply device and varies in a range from 0 V to a burn-in voltage;

a charge/discharge step of charging a load capacitor of an internal circuit of the semiconductor chip by using the pulse voltage if an input signal supplied to the semiconductor chip is at the burn-in voltage, and discharging the load capacitor by using the pulse voltage if the input signal is at 0 V; and

a step of imposing current stress on the internal circuit by using a current generated in said charge/discharge step.

2. The burn-in test method according to claim 1, wherein, in said pulse voltage supplying step, the pulse voltage is varied in a range from a voltage that is higher than or equal to a threshold voltage of the semiconductor chip to the burn-in voltage.

3. The burn-in test method according to claim 2, wherein, in said pulse voltage supplying step, the pulse voltage has a pulse waveform in which a high-voltage period is longer than a low-voltage period.

4. The burn-in test method according to claim 3, further comprising, prior to said pulse voltage supplying step, a step of supplying a test pattern for changing an internal state of the semiconductor chip.

5. The burn-in test method according to claim 1, further comprising, before the pulse voltage supplying step, a step of supplying a test pattern for changing an internal state of the semiconductor chip.

6. The burn-in test method according to claim 2, further comprising, before the pulse voltage supplying step, a step of supplying a test pattern for changing an internal state of the semiconductor chip.

7. A burn-in test apparatus comprising:

a burn-in apparatus having a pulsed power supply device for supplying a pulse voltage that varies in pulse form in a range from 0 V to a burn-in voltage; and

a semiconductor chip that is supplied with the pulse voltage from the pulsed power supply device,

wherein said semiconductor chip has an internal circuit and a load capacitor in said internal circuit, said internal circuit being given current stress in such a manner that a current is caused to flow through said internal circuit by charging said load capacitor when an input signal supplied to said semiconductor chip is at the burn-in voltage, and discharging said load capacitor when the input signal is at 0 V.

8. The burn-in test apparatus according to claim 7, wherein the pulse voltage is varied in pulse form in a range from a voltage that is higher than or equal to a threshold voltage of said semiconductor chip to the burn-in voltage.

9. The burn-in test apparatus according to claim 8, wherein the pulse voltage has a pulse waveform in which a high-voltage period is longer than a low-voltage period.

10. The burn-in test apparatus according to claim 9, wherein said burn-in apparatus supplies a test pattern for changing an internal state of the semiconductor chip.

11. The burn-in test apparatus according to claim 7, wherein said burn-in apparatus supplies a test pattern for changing an internal state of said semiconductor chip.

12. The burn-in test apparatus according to claim 8, wherein said burn-in apparatus supplies a test pattern for changing an internal state of the semiconductor chip.

14. The burn-in test apparatus according to claim 13, wherein the pulse voltage is varied in pulse form in a range from a voltage that is higher than or equal to a threshold voltage of said semiconductor chip to the burn-in voltage.

15. The burn-in test apparatus according to claim 14, wherein the pulse voltage has a pulse waveform in which a high-voltage period is longer than a low-voltage period.

16. The burn-in test apparatus according to claim 15, wherein said burn-in apparatus supplies a test pattern for changing an internal state of said semiconductor chip.

17. The burn-in test apparatus according to claim 13, wherein said burn-in apparatus supplies a test pattern for changing an internal state of said semiconductor chip.

18. The burn-in test apparatus according to claim 14, wherein said burn-in apparatus supplies a test pattern for changing an internal state of said semiconductor chip.

13. A burn-in test apparatus comprising:

a burn-in apparatus having;

a plurality of DC power supply devices for supplying respective DC voltages; and

a burn-in control signal generation device for generating a burn-in control signal to be used for selecting one of said DC power supply devices; and

a semiconductor chip that is supplied with the DC voltages from said respective DC power supply devices, said semiconductor chip having;

a plurality of pulsed power supply devices for supplying respective pulse voltages that vary in pulse form in a range from 0 V to a burn-in voltage;

an addition section for generating a plurality of pulse supply voltages by adding the DC voltages to the pulse voltages, respectively;

a selection circuit for selecting one of the pulse supply voltages generated by said addition section in accordance with the burn-in control signal; and

an internal circuit including a load capacitor,

wherein the internal circuit being given current stress in such a manner that a current is caused to flow through said internal circuit by charging said load capacitor by using the selected pulse supply voltage when an input signal supplied to said semiconductor chip is at the burn-in voltage, and discharging said load capacitor by using the pulse supply voltage when the input signal is at 0 V.