High speed video frame buffer

• US 20020050959A1
• Filed: 08/21/2001
• Published: 05/02/2002
• Est. Priority Date: 04/11/1997
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Clifford Whitmore, Farmer Michael, James Deming, Mark Mosley, Matt Buckelew, Steven Heinrich, Stewart Carlton
• Inventors: Farmer, Michael, Mosley, Mark, Deming, James, Carlton, Stewart, Buckelew, Matt, Heinrich, Steven, Whitmore, Clifford
• Granted Patent: US 6,667,744 B2
• Time in Patent Office: Days
• US Class Current: 345/55
• CPC Class Codes: G09G 2360/12 Frame memory handling
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/122 Tiling
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G11C 7/1015 Read-write modes for single port memories, i.e. having either a random port or a serial port
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

A device for storing pixel information for displaying a graphics image on a display includes a frame buffer and a processor. The information includes an intensity value and a value associated with each of a plurality of additional planes for each pixel. The frame buffer memory has a series of consecutive addresses for storing information to be output to the display. The frame buffer may be subdivided into a plurality of blocks, where each block corresponds to a region of the display having a plurality of contiguous pixels. The processor places the pixel information within the frame buffer memory so that in a given block there are placed at a first collection of consecutive addresses the intensity values for each of the pixels in the block.

Claims

1. An apparatus for displaying a graphical image on a display device having a plurality of pixels, the apparatus comprising:

a frame buffer having a plurality of consecutive address locations for storing graphical image data associated with the graphical image; and

a processor having an output that directs a message to the frame buffer, the message including the graphical image data for two or more pixels on the display device, the graphical image data in the message including intensity data and other data, the processor storing the intensity data for the two or more pixels in the frame buffer in a first set of consecutive address locations in the frame buffer.

2. The apparatus as defined by claim 1 wherein the processor stores the other data for the two or more pixels in the frame buffer in a second set of address locations in the frame buffer.

3. The apparatus as defined by claim 1 wherein the intensity data includes data relating to at least one of the colors of red, blue, and green.

4. The apparatus as defined by claim 1 wherein the other data includes depth data.

5. The apparatus as defined by claim 1 wherein the other data is stored in a second set of consecutive address locations in the frame buffer, the first set of address locations immediately preceding the second set of address locations.

6. The apparatus as defined by claim 1 wherein the processor is a resolver.

7. The apparatus as defined by claim 1 wherein the frame buffer includes a plurality of banks, the intensity data being stored in a single bank.

8. A method of storing image data in a frame buffer for display on a display device, the frame buffer having a plurality of consecutive address locations. the display device having a plurality of pixels, the method comprising:

retrieving intensity data and other data for two or more pixels on the display device;

storing the retrieved intensity data in a first set of consecutive address locations in the frame buffer; and

storing the retrieved other data in other address locations in the frame buffer.

9. The method as defined by claim 8 wherein the other address locations are consecutive.

10. An apparatus for displaying a graphical image on a display device having a plurality of pixels, the apparatus comprising:

a frame buffer that stores image data associated with the graphical image, the frame buffer including a plurality of consecutive address locations; and

a first processor that processes image data for a first set of stripes, each stripe in the first set of stripes being a plurality of contiguous pixels on the display device, each stripe in the first set of stripes being noncontiguous with the other stripes in the first set of stripes,

the first processor placing the image data for the first set of stripes in a first set of consecutive address locations in the frame buffer.

11. The apparatus as defined by claim 10 further comprising:

a second processor that processes image data for a second set of stripes, each stripe in the second set of stripes being a plurality of contiguous pixels on the display device, each stripe in the second set of stripes being noncontiguous with the other stripes in the second set of stripes,

the second processor storing the image data for the second set of stripes in a second set of consecutive address locations in the frame buffer,

the first set of stripes having no common stripes with the second set of stripes.

12. The apparatus as defined by claim 11 wherein the first processor and the second processor are resolvers.

13. The apparatus as defined by claim 10 wherein the first set of consecutive address locations includes-consecutively stored intensity data.

15. The apparatus as defined by claim 14 further comprising a third processor that processes graphical image data for a third set of stripes, each stripe in the third set of stripes being a plurality of contiguous pixels within a single one of the pixel blocks,

the first, second and third processors processing different stripes in a given pixel block.

17. The method as defined by claim 16 wherein the stripes are 8-by-1 pixel wide.

19. The apparatus as defined by claim 18 wherein the processor includes a closer that closes the first bank while the second set of graphical data is being stored in the second bank.

20. The apparatus as defined by claim 19 wherein the frame buffer has a plurality of consecutive address locations for storing the graphical data, and

the processor includes an output that directs a message to the frame buffer, the message including the graphical data for two or more pixels on the display device, the graphical data in the message including intensity data and other data, the processor storing the intensity data for the two or more pixels in the frame buffer in a first set of consecutive address locations in the frame buffer.

21. The apparatus as defined by claim 18 wherein the processor is a resolver.

22. The apparatus as defined by claim 18 wherein the processor is a single port processor.

24. The device as defined by claim 23 wherein the processor further includes an arrangement for placing the other data for the set of two or more of the pixels at a second set of consecutive addresses in the frame buffer, the second set of consecutive addresses and first set of consecutive addresses being within the given block.

25. The device as defined by claim 23 wherein the intensity value includes color data.

14. An apparatus for displaying a graphical image on a display device having a plurality of pixels, the display defining a plurality of contiguous pixel blocks that each include a plurality of contiguous pixels, the apparatus comprising:

a first processor that processes graphical image data for a first set of stripes, each stripe in the first set of stripes being a plurality of contiguous pixels within a single one of the pixel blocks; and

a second processor that processes graphical image data for a second set of stripes, each stripe in the second set of stripes being a plurality of contiguous pixels within a single one of the pixel blocks;

the first processor and second processor processing different stripes in a given pixel block.

16. A method of processing graphical image data for display on a display device having a plurality of pixels, the method comprising:

dividing the display device into a plurality of blocks, each block including a plurality of contiguous pixels;

defining a plurality of stripes within each of the plurality of blocks;

assigning a first set of stripes to a first processor;

assigning a second set of stripes to a second processor, the first set of stripes having no common stripes with the second set of stripes,

controlling the first processor to process the first set of stripes; and

controlling the second processor to process the second set of stripes.

18. An apparatus for displaying a graphical image on a display device, the apparatus comprising:

a frame buffer for storing graphical data relating to the graphical image, the frame buffer including a first bank for storing a first set of graphical data, and a second bank for storing a second set of graphical data, the first bank and second bank being separately addressable; and

a processor that directs the graphical data to the frame buffer for storage, the processor including an opener that opens the second bank while the first set of graphical data is being stored in the first bank.

23. A device for storing pixel information for displaying a graphics image on a display, the information including an intensity value and other data, the device comprising:

a frame buffer memory having a series of consecutive addresses for storing information to be output to the display, the frame buffer being subdivided into a plurality of blocks; and

a processor for placing the pixel information within the frame buffer memory, the processor placing the intensity values for a set of two or more of the pixels at a first set of consecutive addresses in a given block of the frame buffer.

26. A device for storing pixel information for displaying a graphics image on a display, the information including an intensity value and a value associated with each of a plurality of additional planes for each pixel, the device comprising:

a frame buffer for storing information to be output to the display, the frame buffer having a plurality of banks, each bank being separately addressable and being subdivided into a plurality of stripes, each stripe corresponding to a region of the display having a plurality of contiguous pixels; and

a processor for placing the pixel information within the frame buffer so that pixel information relating to first and second contiguous stripes is stored in different ones of the plurality of banks.