Semiconductor device and method of manufacturing same

• US 20020052086A1
• Filed: 04/12/2001
• Published: 05/02/2002
• Est. Priority Date: 10/31/2000
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Maeda, Shigenobu
• Granted Patent: US 6,512,258 B2
• Time in Patent Office: Days
• US Class Current: 438/283
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

Provided are a semiconductor device that optimizes the operation characteristics such as of both an insulating gate type transistor for high voltage and an insulating gate type transistor for low voltage, and a method of manufacturing the same. Specifically, a patterned resist (25) is formed so as to cover a low voltage operation region (A2), a second LDD implantation process of implanting an impurity ion (14) by using the resist (25) as a mask, is performed over a silicon oxide film (6) thereby to form an impurity diffusion region (13) in the surface of a semiconductor substrate (1) in a high voltage operation region (A1). After this step, the silicon oxide film (6) in the high voltage operation region (A1) contains the impurity during the second LDD implantation process whereas the silicon oxide film (6) in a low voltage operation region (A2) contains no impurity. This leads to such a characteristic that in the following pre-treatment with a wet process, the silicon oxide film (6) containing the impurity in the high voltage operation region (A1) is reduced in thickness, and the silicon oxide film (6) containing no impurity in the low voltage operation region (A2) is not reduced in thickness.

Claims

1. A semiconductor device containing first and second transistors of an insulating gate type formed in a semiconductor substrate,

each of said first and second transistors comprising:

a gate insulating film selectively disposed on said semiconductor substrate, the surface of said semiconductor substrate underlying said gate insulating film being defined as a channel region;

a gate electrode disposed on said gate insulating film;

a sidewall disposed adjacent to the side surface of said gate electrode; and

a source/drain region disposed in the surface of said semiconductor substrate with said channel region interposed therebetween,

wherein said sidewall of said first transistor has a smaller forming width and a smaller forming height than said sidewall of said second transistor.

2. The semiconductor device according to claim 1, wherein

said sidewalls of said first and second transistors have a lower layer sidewall disposed on the side surface of said gate electrode and on the surface of said semiconductor substrate, and have an upper layer sidewall disposed on said lower layer sidewall,

a film thickness of said lower layer sidewall of said sidewall of said first transistor is smaller than a film thickness of said lower layer sidewall of said second transistor.

3. The semiconductor device according to claim 2, wherein

a recessed amount of the end portion of said lower layer sidewall from the end portion of said upper layer sidewall toward said gate electrode in said first transistor is larger than a recessed amount of the end portion of said lower layer sidewall from the end portion of said upper layer sidewall toward said gate electrode in said second transistor, and

a forming length of said source/drain region from the end portion of said sidewall to said gate electrode in said first transistor is larger than a forming length of said source/drain region from the end portion of said sidewall to said gate electrode in said second transistor.

4. The semiconductor device according to claim 2, wherein

the film thickness of said lower layer sidewall of said first transistor includes a first film thickness in the area adjacent to the side surface of said gate electrode and a second film thickness in the area on the surface of said semiconductor substrate, and

said first film thickness is smaller than said second film thickness or reduces to zero.

5. The semiconductor device according to claim 1, wherein

said sidewall wall of said second transistor has a lower layer sidewall disposed on the side surface of said gate electrode and on the surface of said semiconductor substrate, and has an upper layer sidewall disposed on said lower layer sidewall, and

said sidewall of said first transistor includes a sidewall, the shape of which is substantially the same as said upper layer sidewall of said second transistor.

6. The semiconductor device according to claim 5, wherein

said sidewall of said first transistor has a thermal oxide film in its undermost layer.

7. The semiconductor device according to claim 1, wherein

said semiconductor substrate includes a SOI substrate comprising a substrate, at least the surface of which is insulative, and a semiconductor layer disposed on the surface of said substrate.

8. The semiconductor device according to claim 1, wherein

the conductivity type of said first and second transistors includes an N type.

9. The semiconductor device according to claim 1, wherein

the conductivity type of said first and second transistors includes a P type.

10. A method of manufacturing a semiconductor device containing first and second transistors of an insulating gate type formed in a semiconductor substrate, comprising the steps of:

(a) forming first and second gate insulating films in first and second regions on said semiconductor substrate, respectively, the surface of said semiconductor substrate under said first and second gate insulating films being defined as first and second channel regions, respectively;

(b) forming first and second gate electrodes on said first and second gate insulating films, respectively;

(c) forming a second impurity diffusion region by introducing impurity only to said second region by using said second gate electrode as a mask;

(d) forming a lower layer sidewall film on the entire surface;

(e) forming a first impurity diffusion region by introducing impurity only to said first region over said lower layer sidewall film by using said first gate electrode as a mask;

(f) forming an upper layer sidewall film on the entire surface;

(g) performing an etch back process to said upper layer sidewall film so that on the side surfaces of said first and second gate electrodes, first and second upper layer sidewalls are formed with said lower layer sidewall film interposed therebetween;

(h) selectively removing said lower layer sidewall film to form first and second lower layer sidewalls on the side surfaces of said first and second gate electrodes and on the surface of said semiconductor substrate beneath said first and second upper layer sidewalls; and

(i) forming a first source/drain region by introducing impurity by using said first upper layer and lower layer sidewalls and said first gate electrode as a mask, and forming a second source/drain region by introducing impurity by using said second upper layer and lower layer sidewalls and said second gate electrode as a mask, said first impurity diffusion region adjacent to said first source/drain region in the direction of said first gate electrode being defined as a first LDD region, said second impurity diffusion region adjacent to said second source/drain region in the direction of said second gate electrode being defined as a second LDD region,

wherein said first transistor comprises said first gate insulating film, said first gate electrode, said first upper layer sidewall, said first lower layer sidewall, said first source/drain region and said first LDD region, and said second transistor comprises said second gate insulating film, said second gate electrode, said second upper layer sidewall, said second lower layer sidewall, said second source/drain region and said second LDD region.

11. The method of manufacturing a semiconductor device according to claim 10, wherein

said first transistor includes a NMOS transistor for high voltage, and

said second transistor includes a NMOS transistor for low voltage, a PMOS transistor for low voltage and a PMOS transistor for high voltage.

12. The method of manufacturing a semiconductor device according to claim 10, wherein

said first transistor includes a NMOS transistor for high voltage and a PMOS transistor for high voltage, and

said second transistor includes a NMOS transistor for low voltage and a PMOS transistor for low voltage.

13. The method of manufacturing a semiconductor device according to claim 10, wherein

said first transistor includes a NMOS transistor for high voltage and a PMOS transistor for low voltage, and

said second transistor includes an NMOS transistor for low voltage and a PMOS transistor for high voltage.

14. The method of manufacturing a semiconductor device according to claim 10, wherein

said first transistor includes a NMOS transistor for high voltage, a PMOS transistor for high voltage and a PMOS transistor for low voltage, and

said second transistor includes a NMOS transistor for low voltage.

15. The method of manufacturing a semiconductor device according to claim 10, further comprising the step of:

(j) performing, before said step (d), a RTA (rapid thermal annealing) process.

16. The method of manufacturing a semiconductor device according to claim 10, wherein

said step (d) includes the step of forming said lower layer sidewall film by using TEOS as a material.

17. The method of manufacturing a semiconductor device according to claim 10, wherein

said step (d) includes the step of forming said lower layer sidewall film by using a high temperature CVD thermal film as a material.

18. The method of manufacturing a semiconductor device according to claim 10, further comprising the step of:

(k) performing, between said steps (e) and (f), a pre-treatment with a wet process.

19. The method of manufacturing a semiconductor device according to claim 18, wherein

said step (h) includes the step of removing said lower layer sidewall film by a wet etching.

20. The method of manufacturing a semiconductor device according to claim 10, wherein

said step (e) includes the step of introducing nitrogen into said first impurity diffusion region.