System for executing virtual machine instructions

• US 20020053072A1
• Filed: 08/29/2001
• Published: 05/02/2002
• Est. Priority Date: 08/31/2000
• Status: Active Grant

• Current Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Lindwer, Menno Menasshe, Steinbusch, Otto Lodewijk
• Granted Patent: US 7,234,134 B2
• Time in Patent Office: Days
• US Class Current: 717/148
• CPC Class Codes: G06F 9/381 Loop buffering
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/45516 Runtime code conversion or optimisation

Abstract

A data processing system has a processor core, memory and a virtual machine interpreter. The virtual machine interpreter receives virtual machine instructions selected dependent on program flow during execution of a virtual machine program. The virtual machine interpreter generates native machine instructions that implement the virtual machine instructions for execution by the processor core. The virtual machine interpreter identifies an initial virtual machine instruction from a body of virtual machine instructions, where the body is expected to be executed repeatedly. The virtual machine interpreter records a correspondence between the initial virtual machine instruction in the body and a memory location in the memory and writes native instructions for the body into the memory from said memory location. The processor core executes the native instructions for the body and repeats execution of the native instructions for the body by executing the written native machine instructions for the body from memory starting from said memory location.

Claims

1. A data processing system for executing a program of virtual machine instructions with a processor core that is arranged to execute native instructions comprising

the processor core;

a memory;

a virtual machine interpreter for receiving virtual machine instructions selected dependent on program flow during execution of the program, the virtual machine interpreter being coupled to the processor core to generate native machine instructions that implement the virtual machine instructions for execution by the processor core, the virtual machine interpreter being arranged

to identify an initial virtual machine instruction from a body of successive ones of the selected virtual machine instructions, where the body is expected to be executed repeatedly;

to record a correspondence between the initial virtual machine instruction in the body and a memory location in the memory;

to write native instructions for the body into the memory from said memory location, the native instructions for the body being generated for virtual machine instructions starting from the initial virtual machine instruction;

to cause the processor core to execute the native instructions for the body and to repeat execution of the native instructions for the body by executing the written native machine instructions for the body from memory starting from said memory location.

2. A data processing system according to claim 1, the virtual machine interpreter being arranged to generate a native branch back instruction to the a start of the body and placing the native branch back instruction at the end of the body in the memory.

3. A data processing system according to claim 2, the virtual machine interpreter being arranged to place an unconditional further native branch instruction behind the native branch instruction, the unconditional further native branch instruction having a target address in a range of addresses that does not overlap a further range of addresses in which the body is stored, the virtual machine interpreter being arranged to monitor a program counter address of the processor core and to resume selection of the virtual machine instructions and generation of native machine instructions from the selected virtual machine instructions when the program counter address enters said range of addresses after execution of the loop body.

4. A data processing system according to claim 1, the virtual machine interpreter being arranged to receive hint information, which does not affect program flow, the hint information indicating at least said initial virtual machine instruction, the virtual machine interpreter recording said correspondence and writing the native instructions for the body when program flow reaches the initial virtual machine instruction, conditional upon receiving said hint information.

8. A method according to claim 4, said identifying comprising preprocessing the program to detect loop terminating with a virtual branch back instruction and adding a hint to the program which identifies a target address of the virtual branch back instruction as the initial virtual machine instruction.

5. A method of executing a program of virtual machine instructions with a processor core that is arranged to execute native instructions, the method comprising

selecting, under control of program flow, virtual machine instructions to be executed;

determining native instructions from the selected virtual machine instructions, to implement the selected virtual machine instructions;

identifying an initial virtual machine instruction from a body of successive ones of the selected virtual machine instructions that is expected to be executed repeatedly;

recording a correspondence between the initial virtual machine instruction and a memory location;

writing native instructions for the body into a memory from said memory location, the native instructions for the body being determined from virtual machine instructions starting from the initial virtual machine instruction;

causing the processor core to execute the native instructions for the body and to repeat execution of the native instructions for the body by executing the written native machine instructions for the body from memory starting from said memory location.

6. A method according to claim 5, comprising generating a native branch back instruction to a start of the body and placing the native branch back instruction at the end of the loop body in the memory.

7. A method according to claim 6, comprising placing an unconditional further native branch instruction behind the native branch instruction, the unconditional further native branch instruction having a target address in a range of addresses that does not overlap a further range of addresses in which the body is stored, the method comprising the step of monitoring a program counter address of the processor core and to resume said selecting and determining when the program counter address enters said range of addresses after execution of the loop body.