Low voltage rail-to-rail CMOS input stage

• US 20020053948A1
• Filed: 12/10/2001
• Published: 05/09/2002
• Est. Priority Date: 02/29/2000
• Status: Active Grant

• Current Assignee: SMSC Analog Technology Center, Inc. (Microchip Technology Incorporated), Seiko Instruments Incorporated (Seiko Group)
• Original Assignee: SMSC Analog Technology Center, Inc. (Microchip Technology Incorporated)
• Inventors: Stockstad, Troy L.
• Granted Patent: US 6,870,422 B2
• Time in Patent Office: Days
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/45342 the AAC comprising control means on a back gate of the AAC
• CPC Class Codes: H03F 2203/45612 the IC comprising one or more input source followers as input stages in the IC
• CPC Class Codes: H03F 3/45192 Folded cascode stages

Abstract

The present invention discloses a low voltage rail-to-rail CMOS input stage. The input stage includes a differential pail of P-channel metal oxide semiconductor field effect (PMOS) transistors, which produces differential output current signal. The input stage further includes a pair of N-channel depletion-mode metal oxide semiconductor field effect (NMOS) transistors, coupled to the bulk terminals of the differential pair of PMOS transistors, for receiving an input signal. The depletion-mode NMOS transistors further act as source follower devices to drive the bulk terminals of the differential pair of PMOS transistors.

Claims

1. A low voltage operational amplifier input stage, the input stage comprising:

a differential pair of P-channel metal oxide semiconductor field effect (PMOS) transistors, each PMOS transistor having a bulk terminal, wherein the PMOS transistors produce a first and a second current signal; and

a pair of N-channel depletion-mode metal oxide semiconductor field effect (NMOS) transistors coupled to the bulk terminals of the differential pair of PMOS transistors for receiving an input signal and for acting as source follower devices to drive the bulk terminals of the differential pair of PMOS transistors.

2. An input stage as recited in claim 1, wherein the input signal is a differential input signal that is coupled to gate terminals of the depletion-mode NMOS transistors.

3. An input stage as recited in claim 1, wherein gate terminals of the differential pair of PMOS transistors are coupled to ground, and wherein source terminals the differential pair of PMOS transistors are coupled to a current source.

4. An input stage as recited in claim 1, wherein the bulk terminals of the depletion-mode NMOS transistors are coupled to ground reference, and the drain terminals of the depletion-mode NMOS transistors are coupled to V_CC.

5. An input stage as recited in claim 4, wherein the source terminals of the depletion-mode NMOS transistors are coupled to the bulk terminals of the differential pair of PMOS transistors.

6. An input stage as recited in claim 1, wherein the source terminal of each of the depletion-mode NMOS transistors has a voltage greater than V_EE when the gate voltage of each of the depletion-mode NMOS transistors has a voltage equal to V_EE.

7. An input stage as recited in claim 6, wherein the source terminal of each of the depletion-mode NMOS transistors has a voltage less than V_CC when the gate voltage of each of the depletion-mode NMOS transistors has a voltage equal to V_CC.

14. A method as recited in claim 6, wherein the source terminal of each of the depletion-mode NMOS transistors has a voltage less than V_CC when the gate voltage of each of the depletion-mode NMOS transistors has a voltage equal to V_CC.

8. A method for providing an output signal from an input stage of a low voltage operation amplifier, the method comprising the operations of:

providing an input signal to a pair of N-channel depletion-mode metal oxide semiconductor field effect (NMOS) transistors coupled to bulk terminals of a differential pair of P-channel metal oxide semiconductor field effect (PMOS) transistors; and

providing a differential output current signal using the differential pair of PMOS transistors.

9. A method as recited in claim 8, wherein the operation of providing an input signal to the depletion-mode NMOS transistors includes applying a differential input signal to gate terminals of the depletion-mode NMOS transistors.

10. A method as recited in claim 8, wherein gate terminals of the differential pair of PMOS transistors are coupled to ground, and wherein source terminals the differential pair of PMOS transistors are coupled to a current source.

11. A method as recited in claim 8, wherein the bulk terminals of the depletion-mode NMOS transistors are coupled to V_EE, and the drain terminals of the depletion-mode NMOS transistors are coupled to V_CC.

12. A method as recited in claim 11, wherein the source terminals of the depletion-mode NMOS transistors are coupled to the bulk terminals of the differential pair of PMOS transistors.

13. A method as recited in claim 8, wherein the source terminal of each of the depletion-mode NMOS transistors has a voltage greater than V_EE when the gate voltage of each of the depletion-mode NMOS transistors has a voltage equal to V_EE.

16. An ASIC as recited in claim 15, wherein the input signal is a differential input signal that is coupled to gate terminals of the depletion-mode NMOS transistors.

17. An ASIC as recited in claim 15, wherein gate terminals of the differential pair of PMOS transistors are coupled to V_EE, and wherein source terminals the differential pair of PMOS transistors are coupled to a current source.

18. An ASIC as recited in claim 15, wherein the bulk terminals of the depletion-mode NMOS transistors are coupled to ground reference, and the drain terminals of the depletion-mode NMOS transistors are coupled to V_CC.

19. An ASIC as recited in claim 18, wherein the source terminals of the depletion-mode NMOS transistors are coupled to the bulk terminals of the differential pair of PMOS transistors.

20. An ASIC as recited in claim 15, wherein the source terminal of each of the depletion-mode NMOS transistors has a voltage greater than V_EE when the gate voltage of each of the depletion-mode NMOS transistors has a voltage equal to V_EE.

21. An ASIC as recited in claim 20, wherein the source terminal of each of the differential pair of depletion-mode NMOS transistors has a voltage less than V_CC when the gate voltage of each of the differential pair of depletion-mode NMOS transistors has a voltage equal to V_CC.

15. An application specific integrated circuit (ASIC) having an input stage for a low voltage operational amplifier input stage, the ASIC comprising:

a differential pair of P-channel metal oxide semiconductor field effect (PMOS) transistors, each PMOS transistor having a bulk terminal, wherein the PMOS transistors produce a differential current signal; and

a pair of N-channel depletion-mode metal oxide semiconductor field effect (NMOS) transistors coupled to the bulk terminals of the differential pair of PMOS transistors for receiving an input signal and for acting as source follower devices to drive the bulk terminals of the differential pair of PMOS transistors.

22. An operational amplifier input stage, the input stage comprising:

a voltage input network, wherein the voltage input network receives a differential input signal, and wherein the voltage input network provides a voltage input network output signal, the voltage input network output signal being above V_EE when the differential input signal is at V_EE; and

an transconductance network, wherein the transconductance network receives the voltage input network output signal, and wherein the transconductance network provides a differential output signal.

23. An operational amplifier input stage as recited in claim 22, wherein the voltage input network includes a pair of depletion-mode NMOS transistors.

24. An operational amplifier input stage as recited in claim 23, wherein the transconductance network includes a differential pair of PMOS transistors, each PMOS transistor having a bulk terminal.

25. An operational amplifier input stage as recited in claim 24, wherein the depletion-mode NMOS transistors drive the bulk terminals of the differential pair of PMOS transistors.

26. An operational amplifier input stage as recited in claim 22, wherein a source terminal of each of the depletion-mode NMOS transistors has a voltage greater than V_EE when a gate voltage of each of the depletion-mode NMOS transistors has a voltage equal to V_EE.

27. An operational amplifier input stage as recited in claim 26, wherein the source terminal of each of the depletion-mode NMOS transistors has a voltage less than V_CC when the gate voltage of each of the depletion-mode NMOS transistors has a voltage equal to V_CC.

29. A operational amplifier as recited in claim 28, wherein each the PMOS transistor includes a bulk terminal, and wherein the differential pair of PMOS transistors produces a differential output signal.

30. An operational amplifier as recited claim 29, wherein the NMOS transistors are depletion-mode NMOS transistors, and wherein the of depletion-mode NMOS transistors are coupled to the bulk terminals of the differential pair of PMOS transistors.

31. An operational amplifier as recited in claim 30, wherein the depletion-mode NMOS transistors receive a differential input signal using the gate terminals of the NMOS transistors.

32. An operational amplifier as recited in claim 30, wherein the PMOS transistors are coupled to a folded cascode circuit.

33. An operational amplifier as recited in claim 32, wherein the folded cascode circuit includes a pair of NMOS transistors.

35. An input stage as recited in claim 34, wherein the input signal is a differential input signal that is coupled to gate terminals of the depletion-mode PMOS transistors.

36. An input stage as recited in claim 34, wherein gate terminals of the differential pair of NMOS transistors are coupled to V_CC, and wherein source terminals the differential pair of PMOS transistors is coupled to a current source.

37. An input stage as recited in claim 34, wherein the drain terminals of the depletion-mode PMOS transistors are coupled to V_EE.

38. An input stage as recited in claim 37, wherein the source terminals of the depletion-mode PMOS transistors are coupled to the bulk terminals of the differential pair of NMOS transistors.

28. An operational amplifier capable of operating on low supply voltages, the operational amplifier comprising:

an input stage having a differential pair of PMOS transistors, and a pair of NMOS transistors; and

an output stage.

34. A low voltage operational amplifier input stage, the input stage comprising:

a differential pair of N-channel metal oxide semiconductor field effect (NMOS) transistors, each NMOS transistor having a bulk terminal, wherein the NMOS transistors produce a first and a second current signal; and

a pair of P-channel depletion-mode metal oxide semiconductor field effect (PMOS) transistors coupled to the bulk terminals of the differential pair of NMOS transistors for receiving an input signal and for acting as source follower devices to drive the bulk terminals of the differential pair of NMOS transistors.

39. A low voltage operational amplifier input stage, the input stage comprising:

a differential pair of N-channel metal oxide semiconductor field effect (NMOS) transistors, each NMOS transistor having a bulk terminal, wherein the NMOS transistors produce a first and a second current signal; and

a pair of JFET transistors coupled to the bulk terminals of the differential pair of NMOS transistors for receiving an input signal and for acting as source follower devices to drive the bulk terminals of the differential pair of NMOS transistors.