Programmable broadband downstream module

• US 20020056143A1
• Filed: 03/29/2001
• Published: 05/09/2002
• Est. Priority Date: 09/28/1998
• Status: Abandoned Application

• Current Assignee: Coax Corporation
• Original Assignee: Coax Corporation
• Inventors: Darnall, William H., Hodge, Winston W.
• Application Number:
  US09/823,197
• Publication Number:
  US 20020056143A1
• Time in Patent Office: Days
• US Class Current: 725/153
• CPC Class Codes: H04N 21/23406 involving management of server-side video buffer
• CPC Class Codes: H04N 21/23611 Insertion of stuffing data into a multiplex stream, e.g. to obtain a constant bitrate synchronisation arrangements in time-division multiplex systems using bit stuffing for systems with different or fluctuating information rates H04J3/073
• CPC Class Codes: H04N 21/6118 involving cable transmission, e.g. using a cable modem
• CPC Class Codes: H04N 21/6168 involving cable transmission, e.g. using a cable modem
• CPC Class Codes: H04N 21/64 Addressing network arrangements, protocols or services for addressing or naming H04L61/00; support for multicast or broadcast of one-way stream services H04L65/611
• CPC Class Codes: H04N 7/17336 Handling of requests in head-ends

Abstract

The present invention is a programmable broadband downstream module, comprising, a bus interface, a programmable CPU, and a programmable logic. The bus interface is configured to receive a plurality of control data packets and a plurality of transport packets. The plurality of transport packets include a plurality of video transport packets, a plurality of data transport packets, or a plurality of voice transport packets. The programmable CPU is operatively coupled to the bus interface. Additionally, the programmable CPU is configured to combine the plurality of transport packets to generate a programmable CPU output. The programmable logic is operatively coupled to the programmable CPU and is configured to generate a synchronous output for said plurality of transport packets. In operation, a destination address is provided so that transport packets are submitted to a particular downstream module. The downstream module receives transport packets which are intended for the downstream module. The downstream module processes the transport packets according to the programmable CPU and submits packets to the programmable logic which generates a synchronous output.

Claims

1. A programmable broadband downstream module, comprising:

a bus interface configured to receive a plurality of control data packets and a plurality of transport packets, said plurality of transport packets including;

a plurality of video transport packets communicated asynchronously, a plurality of data transport packets communicated asynchronously, and a plurality of voice transport packets communicated asynchronously;

a programmable CPU operatively coupled to said bus interface, said programmable CPU configured to combine said plurality of transport packets to generate a programmable CPU output; and

a programmable logic operatively coupled to said programmable CPU, said programmable logic configured to generate a synchronous output for said plurality of transport packets.

2. The programmable broadband downstream module of claim 1, further comprising a downstream modulator configured to receive and modulate said synchronous output for downstream transmission, said downstream modulator configured to generate a downstream modulator output.

3. The programmable broadband downstream module of claim 2, further comprising an upconverter operatively coupled to said downstream modulator, said upconverter configured to generate a particular RF frequency output for said downstream modulator output.

4. The programmable broadband downstream module of claim 1, further comprising, a CPU memory support module operatively coupled to said programmable CPU, said CPU memory support module configured to provide memory resources for said plurality of control data packets and said plurality of transport packets.

5. The programmable broadband downstream module of claim 4, further comprising a memory module operatively coupled to said programmable logic, said memory module configured to act as a buffer and store said plurality of transport packets and said plurality of control data packets.

6. The programmable broadband downstream module of claim 1 further comprising an encryption circuit operatively coupled between said programmable logic and said downstream modulator, said encryption circuit configured to encrypt said synchronous output.

7. The programmable broadband downstream module of claim 1 wherein said plurality of transport packets are a plurality of MPEG-2 transport packets.

8. The programmable broadband downstream module of claim 7 wherein said programmable CPU is configured to perform bit-stuffing.

9. The programmable broadband downstream module of claim 8 wherein said programmable CPU is configured to provide for insertion of control data into said plurality of MPEG-2 transport packets.

10. The programmable broadband downstream module of claim 9 wherein said programmable CPU is configured to perform byte insertions.

11. A programmable broadband downstream module, comprising:

a bus interface configured to receive a plurality of control data packets and a plurality of transport packets, said plurality of transport packets including;

a plurality of video transport packets communicated asynchronously, and a plurality of data transport packets communicated asynchronously;

a programmable CPU operatively coupled to said bus interface, said programmable CPU configured to combine said plurality of transport packets to generate a programmable CPU output; and

a programmable logic operatively coupled to said programmable CPU, said programmable logic configured to generate a synchronous output for said plurality of transport packets.

12. The programmable broadband downstream module of claim 11, further comprising a downstream modulator configured to receive and modulate said synchronous output for downstream transmission, said downstream modulator configured to generate a downstream modulator output.

13. The programmable broadband downstream module of claim 12, further comprising an upconverter operatively coupled to said downstream modulator, said upconverter configured to generate a particular RF frequency output for said downstream modulator output.

14. The programmable broadband downstream module of claim 11, further comprising, a CPU memory support module operatively coupled to said programmable CPU, said CPU memory support module configured to provide memory resources for said plurality of control data packets and said plurality of transport packets.

15. The programmable broadband downstream module of claim 14, further comprising a memory module operatively coupled to said programmable logic, said memory module configured to act as a buffer and store said plurality of transport packets and said plurality of control data packets.

17. The programmable broadband downstream module of claim 11 wherein said plurality of transport packets are a plurality of MPEG-2 transport packets.

18. The programmable broadband downstream module of claim 17 wherein said programmable CPU is configured to perform bit-stuffing.

19. The programmable broadband downstream module of claim 18 wherein said programmable CPU is configured to provide for insertion of control data into said plurality of MPEG-2 transport packets.

20. The programmable broadband downstream module of claim 19 wherein said programmable CPU is configured to perform byte insertions.

16. The programmable broadband downstream module of claim 111 further comprising an encryption circuit operatively coupled between said programmable logic and said downstream modulator, said encryption circuit configured to encrypt said synchronous output.

21. A programmable broadband downstream module, comprising:

a bus interface configured to receive a plurality of control data packets and a plurality of transport packets, said plurality of transport packets including;

a plurality of video transport packets communicated asynchronously, and a plurality of voice transport packets communicated asynchronously;

a programmable CPU operatively coupled to said bus interface, said programmable CPU configured to combine said plurality of transport packets to generate a programmable CPU output; and

a programmable logic operatively coupled to said programmable CPU, said programmable logic configured to generate a synchronous output for said plurality of transport packets.

22. The programmable broadband downstream module of claim 21, further comprising a downstream modulator configured to receive and modulate said synchronous output for downstream transmission, said downstream modulator configured to generate a downstream modulator output.

23. The programmable broadband downstream module of claim 22, further comprising an upconverter operatively coupled to said downstream modulator, said upconverter configured to generate a particular RF frequency output for said downstream modulator output.

24. The programmable broadband downstream module of claim 21, further comprising, a CPU memory support module operatively coupled to said programmable CPU, said CPU memory support module configured to provide memory resources for said plurality of control data packets and said plurality of transport packets.

25. The programmable broadband downstream module of claim 24, further comprising a memory module operatively coupled to said programmable logic, said memory module configured to act as a buffer and store said plurality of transport packets and said plurality of control data packets.

26. The programmable broadband downstream module of claim 21 further comprising an encryption circuit operatively coupled between said programmable logic and said downstream modulator, said encryption circuit configured to encrypt said synchronous output.

27. The programmable broadband downstream module of claim 21 wherein said plurality of transport packets are a plurality of MPEG-2 transport packets.

28. The programmable broadband downstream module of claim 27 wherein said programmable CPU is configured to perform bit-stuffing.

29. The programmable broadband downstream module of claim 28 wherein said programmable CPU is configured to provide for insertion of control data into said plurality of MPEG-2 transport packets.

30. The programmable broadband downstream module of claim 29 wherein said programmable CPU is configured to perform byte insertions.

31. A programmable broadband downstream module, comprising:

a bus interface configured to receive a plurality of control data packets and a plurality of transport packets, said plurality of transport packets including;

a plurality of data transport packets communicated asynchronously, and a plurality of voice transport packets communicated asynchronously;

a programmable CPU operatively coupled to said bus interface, said programmable CPU configured to combine said plurality of transport packets to generate a programmable CPU output; and

a programmable logic operatively coupled to said programmable CPU, said programmable logic configured to generate a synchronous output for said plurality of transport packets.

32. The programmable broadband downstream module of claim 31, further comprising a downstream modulator configured to receive and modulate said synchronous output for downstream transmission, said downstream modulator configured to generate a downstream modulator output.

33. The programmable broadband downstream module of claim 32, further comprising an upconverter operatively coupled to said downstream modulator, said upconverter configured to generate a particular RF frequency output for said downstream modulator output.

34. The programmable broadband downstream module of claim 31, further comprising, a CPU memory support module operatively coupled to said programmable CPU, said CPU memory support module configured to provide memory resources for said plurality of control data packets and said plurality of transport packets.

35. The programmable broadband downstream module of claim 34, further comprising a memory module operatively coupled to said programmable logic, said memory module configured to act as a buffer and store said plurality of transport packets and said plurality of control data packets.

36. The programmable broadband downstream module of claim 31 further comprising an encryption circuit operatively coupled between said programmable logic and said downstream modulator, said encryption circuit configured to encrypt said synchronous output.

37. The programmable broadband downstream module of claim 31 wherein said plurality of transport packets are a plurality of MPEG-2 transport packets.

38. The programmable broadband downstream module of claim 37 wherein said programmable CPU is configured to perform bit-stuffing.

39. The programmable broadband downstream module of claim 38 wherein said programmable CPU is configured to provide for insertion of control data into said plurality of MPEG-2 transport packets.

40. The programmable broadband downstream module of claim 39 wherein said programmable CPU is configured to perform byte insertions.