Thin film transistor array, method of producing the same, and display panel using the same

• US 20020056838A1
• Filed: 11/15/2001
• Published: 05/16/2002
• Est. Priority Date: 11/15/2000
• Status: Abandoned Application

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ogawa, Kazufumi
• Application Number:
  US09/987,516
• Publication Number:
  US 20020056838A1
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

By imparting conductivity to specified regions of a semiconductor material film 4 formed over a substrate 2, the semiconductor material film 4, in addition to being processed into channel portions (active layers) 4a, source portions 4b, and drain portions 4c of TFTs, is processed into conductive elements containing pixel electrodes 10 connected to the drain portions 4c. Regions composed of an intrinsic semiconductor to which impurities have not been added serve as the active layers (channel regions) of the TFTs and regions to which impurities have been added serve as conductive elements. When transparent electrodes are formed, an oxide semiconductor is used.

Claims

1. A thin film transistor array comprising:

an insulating substrate;

thin film transistors disposed on the substrate in a matrix, each of the thin film transistors comprising a semiconductor layer having a channel portion, a source portion, and a drain portion;

source signal lines each for supplying a source signal to a given column of the thin film transistors;

gate signal lines each for supplying a gate signal to a given row of the thin film transistors; and

pixel electrodes each connected to the drain portion of one of the thin film transistors;

wherein the pixel electrodes contain a semiconductor material the same as a material of the semiconductor layer of each of the thin film transistors.

2. The thin film transistor array according to claim 1, wherein the semiconductor layer of each of the thin film transistors is integrally formed with one of the pixel electrodes.

3. The thin film transistor array according to claim 1, wherein the semiconductor layers, the pixel electrodes, and insulating elements for separating the pixel electrodes from one another are included in a single semiconductor material film.

4. The thin film transistor array according to claim 1, wherein the semiconductor material is light transmissive.

5. The thin film transistor array according to claim 1, wherein the semiconductor material is an oxide semiconductor.

6. The thin film transistor array according to claim 5, wherein the oxide semiconductor is an oxide selected from the group consisting of zinc oxide, zinc-magnesium oxide, zinc-cadmium oxide, and cadmium oxide.

7. The thin film transistor array according to claim 1, wherein the semiconductor layer of each of the thin film transistors is directly connected to one of the source signal lines.

8. The thin film transistor array according to claim 1, wherein with the exception of regions of intersection between the gate signal lines and the source signal lines, the gate signal lines and the source signal lines comprise a same material and are disposed in a same layer.

9. The thin film transistor array according to claim 8, wherein one of

a) the gate signal lines and b) the source signal lines comprise:

line-shaped members disposed in regions other than the regions of intersection; and

connection members for connecting the line-shaped members, the connection members containing a semiconductor material the same as the semiconductor material contained in the pixel electrodes and the line-shaped members being disposed between the other of the signal lines.

10. The thin film transistor array according to claim 1, wherein the gate signal lines and the source signal lines are insulated from one another in regions of intersection by an insulating oxide film formed on a surface of each of either the gate signal lines or the source signal lines.

11. The thin film transistor array according to claim 1, wherein the pixel electrodes are comb-shaped, and the array further comprises comb-shaped counter electrodes disposed on the substrate, each forming a pair with one of the pixel electrodes.

12. The thin film transistor array according to claim 11, wherein the counter electrodes are disposed in a same layer as a layer of either the gate signal lines or the source signal lines.

13. The thin film transistor array according to claim 12, wherein each of the counter electrodes is disposed in a same layer as a layer of the gate signal lines and has an insulating oxide film on a surface thereof.

14. The thin film transistor array according to claim 11, wherein the counter electrodes are disposed in a layer above a layer of the pixel electrodes with an insulating layer disposed therebetween.

15. The thin film transistor array according to claim 1, wherein the pixel electrodes are light transmissive, and the array further comprises additional pixel electrodes electrically connected to the pixel electrodes, the additional pixel electrodes being light reflective.

16. The thin film transistor array according to claim 1, wherein a gate electrode of each of the thin film transistors has an insulating oxide film on a surface thereof.

17. The thin film transistor array according to claim 1, further comprising an undercoat layer formed over a surface on a side of the substrate having the thin film transistors formed thereon.

19. The thin film transistor array according to claim 18, wherein the source signal lines and the pixel electrodes are composed of aluminum or an aluminum alloy.

20. The thin film transistor array according to claim 18, wherein counter electrodes are disposed in a layer above a layer of the pixel electrodes with an insulating layer disposed therebetween.

21. The thin film transistor array according to claim 18, further comprising an undercoat layer formed over a surface on a side of the substrate having the thin film transistors formed thereon.

18. A thin film transistor array comprising:

an insulating substrate;

thin film transistors disposed on the substrate in a matrix, each of the thin film transistors comprising a semiconductor layer having a channel portion, a source portion, and a drain portion;

source signal lines each for supplying a source signal to a given column of the thin film transistors;

gate signal lines each for supplying a gate signal to a given row of the thin film transistors; and

pixel electrodes each connected to the drain portion of one of the thin film transistors;

wherein the source portions and the drain portions are directly connected to the source signal lines and the pixel electrodes, respectively, the source signal lines and the pixel electrodes being composed of the same material.

22. A method of producing a thin film transistor array, comprising an insulating substrate;

thin film transistors disposed on the substrate in a matrix, each of the thin film transistors comprising a semiconductor layer having a channel portion, a source portion, and a drain portion;

source signal lines each for supplying a source signal to a given column of the thin film transistors;

gate signal lines each for supplying a gate signal to a given row of the thin film transistors; and

pixel electrodes each connected to the drain portion of one of the thin film transistors, the method comprising processing a semiconductor material film formed over the substrate into a plurality of elements including pixel electrodes and a semiconductor layer of each of the thin film transistors by adding a p-type impurity or an n-type impurity to specified regions of the semiconductor material film.

23. The method of producing a thin film transistor array according to claim 22, wherein the semiconductor material film is composed of an oxide semiconductor.

24. The method of producing a thin film transistor array according to claim 23, wherein the oxide semiconductor is an oxide selected from the group consisting of zinc oxide, zinc-magnesium oxide, zinc-cadmium oxide, and cadmium oxide.

25. The method of producing a thin film transistor array according to claim 22, wherein thermal diffusion utilizing, as a diffusion source, a conductive element connected to the semiconductor material film and formed in advance is employed to diffuse a constituent element of the conductive element into specified regions of the semiconductor material film.

26. The method of producing a thin film transistor array according to claim 22, wherein, before the adding of the impurity, the semiconductor material film contains a specified amount of an impurity.

27. A method of producing a thin film transistor array according to claim 22, comprising the steps of:

forming a semiconductor material film over the substrate;

processing the semiconductor material film into a shape containing regions where semiconductor layers of thin film transistors and pixel electrodes connected to the semiconductor layers are to be formed;

forming an insulating layer over the processed semiconductor material film;

forming a metal film over the insulating layer;

processing the metal film into a shape of a) gate electrodes over regions of the semiconductor material film where channel portions are to be formed and b) gate signal lines connected to the gate electrodes;

forming an insulating oxide film over exposed surfaces of the processed metal film to obtain gate electrodes and gate signal lines;

processing the semiconductor material film into channel portions, source portions, drain portions, and pixel electrodes by adding a p-type or n-type impurity to the semiconductor material film using the gate electrodes as a mask;

forming a conductive film over the substrate having the processed semiconductor material film formed thereon; and

processing the conductive film to form source signal lines connected to the source portions.

28. The method of producing a thin film transistor array according to claim 27, wherein in the step of processing the conductive film, the conductive film is processed to also form additional pixel electrodes connected to the pixel electrodes.

29. The method of producing a thin film transistor array according to claim 27, wherein the pixel electrodes are comb-shaped, and in the step of processing the metal film, the metal film is processed to also form comb-shaped counter electrodes, each forming a pair with one of the pixel electrodes.

30. The method of producing a thin film transistor array according to claim 27, wherein the insulating oxide film is formed by anodic oxidation.

31. The method of producing a thin film transistor array according to claim 27, wherein the metal film is composed of aluminum or an aluminum alloy.

32. The method of producing a thin film transistor array according to claim 27, further comprising a step of forming an undercoat layer comprising an inorganic substance over the substrate before the step of forming a semiconductor material film.

33. The method of producing a thin film transistor array according to claim 27, further comprising a step of forming a passivation layer comprising an inorganic substance over the substrate having the source signal lines formed thereon.

34. The method of producing a thin film transistor array according to claim 22, comprising the steps of:

forming a conductive film over the substrate;

processing the conductive film to form gate electrodes of the thin film transistors and gate signal lines connected to the gate electrodes;

forming an insulating film over the substrate having the gate electrodes and the gate signal lines formed thereon;

forming a semiconductor material film over the insulating film;

processing the semiconductor material film into a shape containing regions where semiconductor layers of the thin film transistors and pixel electrodes connected to the semiconductor layers are to be formed;

processing the semiconductor material film into channel portions, source portions, drain portions, and pixel electrodes by adding a p-type or n-type impurity into the semiconductor material film using a mask over regions where the channel portions of the semiconductor layers are to be formed;

forming a conductive film over the substrate having the processed semiconductor material film formed thereon; and

processing the conductive film to form source signal lines connected to the source portions.

35. The method of producing a thin film transistor array according to claim 34, wherein in the step of processing the conductive film, the conductive film is processed to also form additional pixel electrodes connected to the pixel electrodes.

36. The method of producing a thin film transistor array according to claim 34, wherein the pixel electrodes are comb-shaped, and in the step of processing the metal film, the metal film is processed to also form comb-shaped counter electrodes, each forming a pair with one of the pixel electrodes.

37. The method of producing a thin film transistor array according to claim 34, wherein:

the pixel electrodes are comb-shaped; and

the method further comprises;

forming an insulating layer over the substrate having the source signal lines formed thereon; and

forming comb-shaped counter electrodes on the insulating layer, each forming a pair with one of the pixel electrodes.

38. The method of producing a thin film transistor array according to claim 34, further comprising a step of forming an undercoat layer composed of an inorganic substance over the substrate before the step of forming a conductive film.

39. The method of producing a thin film transistor array according to claim 34, further comprising a step of forming a passivation layer composed of an inorganic substance over the substrate having the source signal lines formed thereon.

40. The method of producing a thin film transistor array according to claim 22, comprising the steps of:

forming a metal film over the substrate;

forming an insulating film over the substrate having the metal film formed thereon;

processing the metal film and the insulating film into a pattern substantially corresponding to gate signal lines, gate electrodes connected to the gate signal lines, and components of source signal lines not in regions of intersection with the gate signal lines;

forming an insulating oxide film by oxidizing exposed side surfaces of the metal film from which the gate signal lines and the gate electrodes are to be processed, whereby the gate signal lines and

the gate electrodes are obtained;

forming a semiconductor material film over the substrate;

forming channel portions and pixel electrodes by adding a p-type or n-type impurity to the semiconductor material film using a mask over regions where the channel portions are to be formed, the mask having openings for regions where the pixel electrodes and the members connecting the components of the source signal lines are to be formed.

41. The method of producing a thin film transistor array according to claim 40, wherein:

the pixel electrodes are comb-shaped, and in the step of processing the metal film and the insulating film, the metal film is processed to also form comb-shaped counter electrodes, each forming a pair with one of the pixel electrodes; and

in the step of forming channel regions and pixel electrodes, connecting members for electrically connecting a plurality of the counter electrodes to one another are also formed.

42. The method of producing a thin film transistor array according to claim 40, wherein;

the pixel electrodes are comb-shaped; and

the method further comprises the steps of;

forming a passivation layer over the substrate having the pixel electrodes formed thereon; and

forming counter electrodes on the passivation layer, each forming a pair with one of the pixel electrodes.

43. The method of producing a thin film transistor array according to claim 40, wherein the insulating oxide film is formed by anodic oxidation.

44. The method of producing a thin film transistor array according to claim 40, wherein the metal film is composed of aluminum or an aluminum alloy.

45. The method of producing a thin film transistor array according to claim 40, further comprising a step of forming an undercoat layer composed of an inorganic substance over the substrate before the step of forming a metal film.

46. The method of producing a thin film transistor array according to claim 40, further comprising a step of forming a passivation layer composed of an inorganic substance over the substrate having the pixel electrodes formed thereon.

48. The method of producing a thin film transistor array according to claim 47, comprising the steps of:

forming a semiconductor material film over the substrate;

processing the semiconductor material film into a shape containing regions where semiconductor layers of thin film transistors are to be formed;

forming an insulating layer over the processed semiconductor material film;

forming a metal film over the insulating layer;

processing the metal film into a shape of a) gate electrodes of the thin film transistors over regions of the semiconductor material film where channel portions are to be formed and b) gate signal lines connected to the gate electrodes;

forming an insulating oxide film over exposed surfaces of the processed metal film to obtain gate electrodes and gate signal lines;

processing the semiconductor material film into channel portions, source portions, and drain portions by adding a p-type or n-type impurity to the semiconductor material film using the gate electrodes as a mask;

forming a conductive film over the substrate having the processed semiconductor material film formed thereon; and

processing the conductive film to form source signal lines connected to the source portions and pixel electrodes directly connected to the drain portions.

49. The method of producing a thin film transistor array according to claim 48, wherein the pixel electrodes are comb-shaped;

and

the method further comprises the steps of;

forming an insulating layer over the substrate having the pixel electrodes formed thereon; and

forming comb-shaped counter electrodes, each forming a pair with one of the pixel electrodes, over the insulating layer.

50. The method of producing a thin film transistor array according to claim 48, wherein the insulating oxide film is formed by anodic oxidation.

51. The method of producing a thin film transistor array according to claim 48, wherein the metal film is composed of aluminum or an aluminum alloy.

52. The method of producing a thin film transistor array according to claim 48, further comprising a step of forming an undercoat layer composed of an inorganic substance over the substrate before the step of forming a semiconductor material film over the substrate.

53. The method of producing a thin film transistor array according to claim 48, further comprising a step of forming a passivation layer composed of an inorganic substance over the substrate having the pixel electrodes formed thereon.

54. The method of forming a thin film transistor array according to claim 47, comprising the steps of:

forming a conductive film over the substrate;

processing the conductive film to form gate electrodes of thin film transistors and gate signal lines connected to the gate electrodes;

forming an insulating film over the substrate having the gate electrodes and the signal lines formed thereon;

forming a semiconductor material film over the insulating film;

processing the semiconductor material film into a shape containing regions where the semiconductor layers of the thin film transistors are to be formed;

processing the semiconductor material film into channel portions, source portions, and drain portions by adding a p-type or n-type impurity to the semiconductor material film using a mask over regions where the channel portions of the thin film transistors are to be formed;

forming a conductive film over the substrate having the processed semiconductor material film formed thereon; and

processing the conductive film into a specified pattern to form source signal lines connected to the source portions and pixel electrodes connected to the drain portions.

55. The method of producing a thin film transistor array according to claim 54, wherein the pixel electrodes are comb-shaped;

and

the method further comprises the steps of;

forming an insulating layer over the substrate having the pixel electrodes formed thereon; and

forming comb-shaped counter electrodes on the insulating layer, each forming a pair with one of the pixel electrodes.

56. The method of forming a thin film transistor array according to claim 54, further comprising the step of forming an undercoat layer composed of an inorganic substance over the substrate before the step of forming a conductive film over the substrate.

57. The method of producing a thin film transistor array according to claim 54, further comprising a step of forming a passivation layer composed of an inorganic substance over the substrate having the pixel electrodes formed thereon.

47. A method of producing a thin film transistor array comprising an insulating substrate;

thin film transistors disposed on the substrate in a matrix, each of the thin film transistors comprising a semiconductor layer having a channel portion, a source portion, and a drain portion;

source signal lines each for supplying a source signal to a given column of the thin film transistors;

gate signal lines each for supplying a gate signal to a given row of the thin film transistors; and

pixel electrodes each connected to the drain portion of one of the thin film transistors, wherein source signal lines and pixel electrodes are formed so as to be directly connected to exposed source portions and drain portions of semiconductor layers formed on the substrate.

58. A display panel comprising an array substrate, a counter substrate, and a liquid crystal layer sandwiched between the array substrate and the counter substrate, the array substrate comprising:

an insulating substrate;

thin film transistors disposed on the substrate in a matrix, each of the thin film transistors comprising a semiconductor layer having a channel portion, a source portion, and a drain portion;

source signal lines each for supplying a source signal to a given column of the thin film transistors;

gate signal lines each for supplying a gate signal to a given row of the thin film transistors; and

pixel electrodes each connected to the drain portion of one of the thin film transistors and containing a semiconductor material the same as a material of the semiconductor layer of each of the thin film transistors.

59. A display panel comprising:

an insulating substrate;

thin film transistors disposed on the substrate in a matrix, each of the thin film transistors comprising a semiconductor layer having a channel portion, a source portion, and a drain portion;

source signal lines each for supplying a source signal to a given column of the thin film transistors;

gate signal lines each for supplying a gate signal to a given row of the thin film transistors;

pixel electrodes each connected to the drain portion of one of the thin film transistors and containing a semiconductor material the same as a material of the semiconductor layer of each of the thin film transistors;

an electroluminescent layer stacked on the pixel electrodes; and

a counter electrode stacked on the electroluminescent layer.