Packaged power devices for radio frequency (RF) applications
First Claim
1. An integrated power device, comprising:
- a plurality of field effect transistor cells in an active portion of a semiconductor substrate;
a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;
a gate electrode that is electrically connected to each gate of said plurality of field effect transistor cells and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;
an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode; and
a source electrode that is electrically coupled to each source of said plurality of field effect transistor cells and to said Faraday shield layer.
14 Assignments
0 Petitions
Accused Products
Abstract
Packaged power devices include an electrically conductive flange having a slot therein and an electrically conductive substrate mounted within the slot. A dielectric layer is provided on the electrically conductive substrate and a gate electrode strip line is patterned on the dielectric layer. The gate electrode strip line extends opposite the electrically conductive substrate. A vertical MOSFET is also provided. The vertical MOSFET has a source electrically coupled and mounted to a first portion of the flange located outside the slot and a gate electrode electrically coupled and mounted to a first end of the gate electrode strip line.
-
Citations
83 Claims
-
1. An integrated power device, comprising:
-
a plurality of field effect transistor cells in an active portion of a semiconductor substrate;
a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;
a gate electrode that is electrically connected to each gate of said plurality of field effect transistor cells and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;
an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode; and
a source electrode that is electrically coupled to each source of said plurality of field effect transistor cells and to said Faraday shield layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. An RF power device, comprising:
-
a field effect transistor in an active portion of a semiconductor substrate;
a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;
a gate electrode that is electrically connected to a gate of said field effect transistor and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;
a gate electrode strip line that is electrically connected at a first end to said gate electrode and is substantially confined within the outer perimeter of said Faraday shield layer;
an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode; and
a source electrode that is electrically coupled to a source of said field effect transistor and to said Faraday shield layer. - View Dependent Claims (9, 10, 11, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23, 24, 26, 27, 28, 29, 30, 31, 32, 33, 35, 36, 37, 38, 39, 40)
-
-
12. An RF power device, comprising:
-
a field effect transistor in an active portion of a semiconductor substrate;
a gate electrode that is electrically connected to a gate of said field effect transistor and extends outside a perimeter of the active portion of the semiconductor substrate;
a Faraday shield layer on the semiconductor substrate;
a gate electrode strip line that is electrically connected at a first end to said gate electrode and is substantially confined within an outer perimeter of said Faraday shield layer;
an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode strip line; and
a source electrode that is electrically coupled to a source of said field effect transistor and to said Faraday shield layer.
-
-
15. A semiconductor switching device, comprising:
-
a vertical field effect transistor in an active portion of a semiconductor substrate;
a gate electrode that is electrically connected to a gate of said field effect transistor; and
a Faraday shield layer extending between at least a portion of said gate electrode and a drain of said field effect transistor.
-
-
25. An integrated power device, comprising:
-
a plurality of field effect transistor cells in an active portion of a semiconductor substrate;
a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;
a gate electrode that is electrically connected to each gate of said plurality of field effect transistor cells and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;
an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode;
a gate electrode strip line that extends on the semiconductor substrate and is electrically connected at a first end to said gate electrode;
a gate pad that is electrically connected to a second end of said gate electrode strip line; and
a source electrode that is electrically coupled to each source of said plurality of field effect transistors cells and to said Faraday shield layer.
-
-
34. A RF power device, comprising:
-
a vertical power device in an active portion of a semiconductor substrate;
a gate electrode that is electrically connected to a gate of the vertical power device and extends outside a perimeter of the active portion;
a gate electrode strip line that extends on the semiconductor substrate and has a first end electrically connected to said gate electrode; and
a gate pad that extends on the semiconductor substrate and is electrically connected to a second end of said gate electrode strip line.
-
-
41. An RF power device, comprising:
-
a field effect transistor in an active portion of a semiconductor substrate;
a gate electrode strip line that is electrically connected at a first end to a gate of said field effect transistor;
a gate pad electrically connected to a second end of said gate electrode strip line; and
a Faraday shield layer extending between both said gate electrode strip line and said gate pad and a drain of said field effect transistor so that said gate electrode strip line and said gate pad are capacitively decoupled from the drain. - View Dependent Claims (42)
-
-
43. A semiconductor switching device, comprising:
-
a semiconductor substrate having a first surface thereon and a drift region of first conductivity type therein;
a quad arrangement of trenches that extend into the first surface of said semiconductor substrate and define a drift region mesa therebetween;
a base region of second conductivity type that extends into the drift region and forms a first P-N rectifying junction therewith;
a source region of first conductivity type that extends into the base region and forms a second P-N rectifying junction therewith;
a quad arrangement of insulated electrodes in said quad arrangement of trenches;
an insulated gate on the drift region mesa; and
a source electrode that extends on the first surface and is electrically connected to said source and base regions and to said quad arrangement of insulated electrodes. - View Dependent Claims (44, 45, 46, 47, 48, 49, 50, 51)
-
-
52. A semiconductor switching device, comprising:
-
a semiconductor substrate having a first surface thereon and a drift region of first conductivity type therein;
a quad arrangement of trenches that extend into the first surface of said semiconductor substrate and define a drift region mesa therebetween;
a base region of second conductivity type that extends into the drift region and forms a first P-N rectifying junction therewith;
a source region of first conductivity type that extends into the base region and forms a second P-N rectifying junction therewith;
a quad arrangement of insulated electrodes in said quad arrangement of trenches;
an insulated gate electrode on the first surface;
a Faraday shield layer that extends on the first surface and surrounds said quad arrangement of trenches;
a source electrode that extends on the first surface and is electrically connected to said source and base regions, said quad arrangement of insulated electrodes and said Faraday shield layer. - View Dependent Claims (53, 54)
-
-
55. A packaged power device, comprising:
-
an electrically conductive flange having a slot therein;
an electrically conductive substrate mounted within the slot;
a dielectric layer on said electrically conductive substrate;
a gate electrode strip line that is patterned on said dielectric layer and extends opposite the electrically conductive substrate; and
a vertical power MOSFET having a source electrically coupled and mounted to a first portion of said flange located outside the slot and a gate electrode electrically coupled and mounted to a first end of said gate electrode strip line. - View Dependent Claims (56, 57, 58, 59, 60, 61)
-
-
62. A packaged power transistor, comprising:
-
an electrically conductive flange having a slot therein;
a ceramic substrate mounted within the slot;
a gate electrode strip line that is patterned on said ceramic substrate and extends opposite a bottom of the slot; and
a vertical power MOSFET having a source electrically coupled and mounted to a first portion of said flange located outside the slot and a gate electrode electrically coupled and mounted to a first end of said gate electrode strip line.
-
-
63. A packaged power transistor device, comprising:
-
an electrically conductive flange having a slot therein;
an integrated circuit substrate mounted to a bottom of the slot, said integrated circuit substrate comprising a semiconductor layer that is electrically coupled to said flange, a dielectric layer on the semiconductor layer and a gate interconnect on the dielectric layer, said gate interconnect comprising a gate electrode strip line or a gate metal strap; and
a vertical power MOSFET having a source electrically coupled and mounted to a first portion of said flange located outside the slot and a gate electrode electrically coupled and mounted to the gate interconnect.
-
-
64. A power device, comprising:
-
an electrically conductive plate;
a ceramic insulating layer on a surface of said electrically conductive plate;
a gate electrode strip line extending on said ceramic insulating layer and opposite said electrically conductive plate; and
a vertical power MOSFET having a source electrode electrically coupled to said electrically conductive plate and a gate electrode electrically coupled to an end of said gate electrode strip line. - View Dependent Claims (65, 66, 67, 70)
-
-
68. A power device, comprising:
-
a device package comprising gate and drain terminals and an electrically conductive flange that operates as a source terminal;
an electrically conductive plate mounted to the electrically conductive flange;
a ceramic insulating layer on a surface of said electrically conductive plate;
a gate electrode strip line extending on said ceramic insulating layer and opposite said electrically conductive plate;
a vertical power MOSFET having a source electrode electrically coupled to said electrically conductive plate and a gate electrode electrically coupled to a first end of said gate electrode strip line;
a first electrical connector mounted to the drain terminal of said device package and a drain electrode of said vertical power MOSFET; and
a second electrical connector mounted to the gate terminal of said device package and a second end of said gate electrode strip line.
-
-
69. A vertical power device, comprising:
-
a semiconductor substrate having a drift region of first conductivity type therein extending adjacent a first face thereof;
first and second stripe-shaped trenches that extend in parallel and in a first direction across said semiconductor substrate;
first and second insulated electrodes in the first and second stripe-shaped trenches, respectively;
first and second base regions of second conductivity type that each extend from a sidewall of said first stripe-shaped trench to an opposing sidewall of said second stripe-shaped trench and define a respective P-N junction with the drift region;
first and second source regions of first conductivity type in said first and second base regions, respectively;
a source electrode that extends on the first face and is electrically connected to said first and second insulated electrodes and to said first and second source regions; and
an insulated gate electrode that extends in a second direction across the first face of said semiconductor substrate that is orthogonal to the first direction.
-
-
71. A UMOSFET, comprising:
-
a semiconductor substrate having a drift region of first conductivity type therein;
a first stripe-shaped trench in said semiconductor substrate;
an insulated gate electrode in said first stripe-shaped trench;
a second stripe-shaped trench that extends in said semiconductor substrate in a direction parallel to said first stripe-shaped trench;
an insulated source electrode in said second stripe-shaped trench;
a base region of second conductivity type that extends in the drift region and between opposing sidewalls of said first and second stripe-shaped trenches;
a source region of first conductivity type in said base region; and
a source electrode that extends on said semiconductor substrate and is electrically connected to said source region and to said insulated source electrode. - View Dependent Claims (72, 73)
-
-
74. A UMOSFET, comprising:
-
a semiconductor substrate having a drift region of first conductivity type therein;
first and second trenches that extend in said semiconductor substrate and define a drift region mesa therebetween;
first and second insulated source electrodes in said first and second trenches, respectively; and
a UMOSFET comprising a third trench that is shallower than said first and second trenches, in the drift region mesa. - View Dependent Claims (75, 76, 77, 78, 79)
-
-
80. A method of forming a vertical power device, comprising the steps of:
-
forming first and second deep trenches in a semiconductor substrate having a drift region of first conductivity type therein that extends into a mesa defined between first and second opposing sidewalls of the first and second deep trenches, respectively;
forming a UMOSFET in the mesa; and
forming first and second base shielding regions of second conductivity type that extend into the mesa and are self-aligned with the first and second opposing sidewalls. - View Dependent Claims (81)
-
-
82. A method of forming a vertical MOSFET, comprising the steps of:
-
implanting base region dopants of second conductivity type into an active portion of a semiconductor substrate having a drift region of first conductivity type therein;
forming a first mask having openings therein on the active portion of the semiconductor substrate;
implanting shielding region dopants of second conductivity type into the active portion of the substrate, using the first mask as an implant mask;
driving-in the implanted base and shielding region dopants to define a base region and a plurality of base shielding regions that extend laterally underneath the first mask and vertically through the base region and into the drift region;
etching first and second deep trenches into the semiconductor substrate to define a drift region mesa therebetween, using the first mask as an etching mask;
forming first and second insulated source electrodes in the first and second trenches, respectively;
implanting source region dopants of first conductivity type into the drift region mesa;
driving-in the implanted source region dopants to define a source region in the base region;
forming a shallow trench that extends in the drift region mesa and has a sidewall extending adjacent the base and source regions;
forming an insulated gate electrode in the shallow trench; and
forming a source electrode that electrically connects the first and second insulated source electrodes, the source region and the base region together.
-
-
83. A method of forming a vertical power device, comprising the steps of:
-
forming first and second deep trenches in a semiconductor substrate having a drift region of first conductivity type therein that extends into a mesa defined between first and second opposing sidewalls of the first and second deep trenches, respectively; and
forming a UMOSFET in the mesa.
-
Specification