Vertical power devices having deep and shallow trenches and methods of forming same

• US 20020056884A1
• Filed: 11/05/2001
• Published: 05/16/2002
• Est. Priority Date: 11/16/2000
• Status: Active Grant

• Current Assignee: Silicon Semiconductor Corporation
• Original Assignee: Silicon Semiconductor Corporation
• Inventors: Baliga, Bantval Jayant
• Granted Patent: US 6,649,975 B2
• Time in Patent Office: Days
• US Class Current: 257/492
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/371 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/40095 Kinked
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/73255 Bump and strap connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84 using a strap connector
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/37 of an individual strap connector
• CPC Class Codes: H01L 24/40 of an individual strap connector
• CPC Class Codes: H01L 24/41 of a plurality of strap connectors
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 : of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 : Field plates
• CPC Class Codes: H01L 29/407 : Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 : for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/66712 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13063 : Metal-Semiconductor Field-Effect Transistor [MESFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/1903 : including wave guides
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

Vertical power devices include a semiconductor substrate having a drift region of first conductivity type therein and first and second stripe-shaped trenches that extend in the semiconductor substrate and define a drift region mesa therebetween. First and second insulated source electrodes are provided in the first and second stripe-shaped trenches, respectively. A UMOSFET, comprising a third trench that is shallower than the first and second stripe-shaped trenches, is provided in the drift region mesa.

Claims

1. An integrated power device, comprising:

a plurality of field effect transistor cells in an active portion of a semiconductor substrate;

a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;

a gate electrode that is electrically connected to each gate of said plurality of field effect transistor cells and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;

an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode; and

a source electrode that is electrically coupled to each source of said plurality of field effect transistor cells and to said Faraday shield layer.

2. The device of claim 1, wherein said plurality of field effect transistor cells comprise vertical field effect transistor cells that extend between first and second opposing faces of the semiconductor substrate;

and wherein said Faraday shield layer extends opposite the first face and is separated therefrom by an underlying electrically insulating layer.

3. The device of claim 2, wherein said plurality of field effect transistor cells comprise a drain region extending adjacent the second face of the semiconductor substrate.

4. The device of claim 1, further comprising a gate electrode strip line that is electrically connected to said gate electrode and is at least substantially confined to within the outer perimeter of said Faraday shield layer.

5. The device of claim 3, further comprising an underlying electrically insulating layer extending between said Faraday shield layer and the semiconductor substrate;

and wherein said gate electrode is sufficiently confined within the outer perimeter of said Faraday shield layer that a capacitance between said gate electrode and the drain region is less than about 0.1 times a capacitance between a gate electrode and drain of an otherwise equivalent integrated power device that omits said Faraday shield layer and said intermediate electrically insulating layer from between said gate electrode and said underlying electrically insulating layer.

6. The device of claim 1, further comprising an underlying electrically insulating layer extending between said Faraday shield layer and the semiconductor substrate;

and wherein said gate electrode is sufficiently confined within the outer perimeter of said Faraday shield layer that a capacitance between said gate electrode and the drain region is less than about 0.1 times a capacitance between a gate electrode and drain of an otherwise equivalent integrated power device that omits said Faraday shield layer and said intermediate electrically insulating layer from between said gate electrode and said underlying electrically insulating layer.

7. The device of claim 1, further comprising:

a gate electrode strip line that is confined within the outer perimeter of said Faraday shield layer and has a first end electrically connected to said gate electrode; and

a gate pad that is electrically connected to a second end of said gate electrode strip line.

8. An RF power device, comprising:

a field effect transistor in an active portion of a semiconductor substrate;

a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;

a gate electrode that is electrically connected to a gate of said field effect transistor and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;

a gate electrode strip line that is electrically connected at a first end to said gate electrode and is substantially confined within the outer perimeter of said Faraday shield layer;

an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode; and

a source electrode that is electrically coupled to a source of said field effect transistor and to said Faraday shield layer.

9. The device of claim 8, wherein said intermediate electrically insulating layer extends between said Faraday shield layer and said gate electrode strip line.

10. The device of claim 9, further comprising a gate pad electrically connected to a second end of said gate electrode strip line;

and wherein said intermediate electrically insulating layer extends between said gate pad and said Faraday shield layer.

11. The device of claim 8, further comprising an underlying electrically insulating layer extending between said Faraday shield layer and the semiconductor substrate.

13. The device of claim 12, further comprising a gate pad electrically connected to a second end of said gate electrode strip line;

and wherein said intermediate electrically insulating layer extends between said gate pad and said Faraday shield layer.

14. The device of claim 12, further comprising an underlying electrically insulating layer extending between said Faraday shield layer and the semiconductor substrate.

16. The device of claim 15, wherein said Faraday shield layer is electrically connected to a source of said vertical field effect transistor.

17. The device of claim 16, further comprising a gate electrode strip line that extends on the semiconductor substrate and is electrically connected at a first end to said gate electrode.

18. The device of claim 17, wherein said Faraday shield layer extends between said gate electrode strip line and the drain of said vertical field effect transistor.

19. The device of claim 16, wherein said Faraday shield layer is separated from said gate electrode by an intermediate electrically insulating layer that provides electrostatic discharge protection to said vertical field effect transistor.

20. The device of claim 19, wherein the intermediate electrically insulating layer comprises a plurality of regions of different electrically insulating materials having different breakdown voltage characteristics.

21. The device of claim 17, wherein said Faraday shield layer is separated from said gate electrode by an intermediate electrically insulating layer that provides electrostatic discharge protection to said vertical field effect transistor;

and wherein said gate electrode, the intermediate electrically insulating layer and said Faraday shield layer collectively form a metal oxide varistor.

22. The device of claim 21, wherein said intermediate electrically insulating layer comprises zinc oxide.

23. The device of claim 19, wherein said intermediate electrically insulating layer comprises intrinsic or P-type polycrystalline silicon;

wherein the gate of said field effect transistor is separated from the active portion of the semiconductor substrate by a gate oxide layer; and

wherein a thickness and/or material characteristic of said intermediate electrically insulating layer is such that its breakdown voltage is less than a breakdown voltage of the gate oxide layer.

24. The device of claim 19, wherein said intermediate electrically insulating layer comprises zinc oxide.

26. The device of claim 25, wherein said Faraday shield layer extends between both said gate pad and gate electrode strip line and a drain of said plurality of field effect transistor cells.

27. The device of claim 26, wherein said intermediate electrically insulating layer provides electrostatic discharge protection to said plurality of field effect transistor cells.

28. The device of claim 27, wherein said intermediate electrically insulating layer comprises a plurality of regions of different electrically insulating materials having different breakdown voltage characteristics.

29. The device of claim 27, wherein said gate electrode, said intermediate electrically insulating layer and said Faraday shield layer collectively form a metal oxide varistor.

30. The device of claim 29, wherein said intermediate electrically insulating layer comprises zinc oxide.

31. The device of claim 27, wherein said intermediate electrically insulating layer comprises intrinsic or P-type polycrystalline silicon.

32. The device of claim 27, wherein said plurality of field effect transistor cells comprise vertical field effect transistor cells that extend between first and second opposing faces of the semiconductor substrate;

and wherein said Faraday shield layer extends opposite the first face and is separated therefrom by an underlying electrically insulating layer.

33. The device of claim 32, wherein no portion of said gate electrode extends outside the outer perimeter of said Faraday shield layer.

35. The device of claim 34, further comprising a Faraday shield layer that extends between said gate electrode strip line and the semiconductor substrate.

36. The device of claim 35, wherein said Faraday shield layer extends between said gate electrode and the semiconductor substrate;

and wherein said gate electrode is patterned so that it is substantially confined within an outer perimeter of said Faraday shield layer.

37. The device of claim 35, wherein the vertical power device is an insulated-gate field effect transistor;

and wherein said Faraday shield layer is electrically connected to a source of the insulated-gate field effect transistor.

38. The device of claim 37, further comprising an intermediate electrically insulating layer extending between said Faraday shield layer and said gate electrode strip line;

and wherein said intermediate electrically insulating layer provides electrostatic discharge protection to the insulated-gate field effect transistor.

39. The device of claim 34, further comprising a Faraday shield layer that extends between said gate pad and the semiconductor substrate and is electrically connected to a terminal of said vertical power device.

40. The device of claim 39, further comprising an intermediate electrically insulating layer extending between said Faraday shield layer and said gate pad;

and wherein said intermediate electrically insulating layer provides electrostatic discharge protection to said vertical power device.

12. An RF power device, comprising:

a field effect transistor in an active portion of a semiconductor substrate;

a gate electrode that is electrically connected to a gate of said field effect transistor and extends outside a perimeter of the active portion of the semiconductor substrate;

a Faraday shield layer on the semiconductor substrate;

a gate electrode strip line that is electrically connected at a first end to said gate electrode and is substantially confined within an outer perimeter of said Faraday shield layer;

an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode strip line; and

a source electrode that is electrically coupled to a source of said field effect transistor and to said Faraday shield layer.

15. A semiconductor switching device, comprising:

a vertical field effect transistor in an active portion of a semiconductor substrate;

a gate electrode that is electrically connected to a gate of said field effect transistor; and

a Faraday shield layer extending between at least a portion of said gate electrode and a drain of said field effect transistor.

25. An integrated power device, comprising:

a plurality of field effect transistor cells in an active portion of a semiconductor substrate;

a Faraday shield layer extending on a portion of the semiconductor substrate that is located outside a perimeter of the active portion;

a gate electrode that is electrically connected to each gate of said plurality of field effect transistor cells and extends outside the perimeter of the active portion in a manner that substantially confines it to within an outer perimeter of said Faraday shield layer;

an intermediate electrically insulating layer disposed between said Faraday shield layer and said gate electrode;

a gate electrode strip line that extends on the semiconductor substrate and is electrically connected at a first end to said gate electrode;

a gate pad that is electrically connected to a second end of said gate electrode strip line; and

a source electrode that is electrically coupled to each source of said plurality of field effect transistors cells and to said Faraday shield layer.

34. A RF power device, comprising:

a vertical power device in an active portion of a semiconductor substrate;

a gate electrode that is electrically connected to a gate of the vertical power device and extends outside a perimeter of the active portion;

a gate electrode strip line that extends on the semiconductor substrate and has a first end electrically connected to said gate electrode; and

a gate pad that extends on the semiconductor substrate and is electrically connected to a second end of said gate electrode strip line.

41. An RF power device, comprising:

a field effect transistor in an active portion of a semiconductor substrate;

a gate electrode strip line that is electrically connected at a first end to a gate of said field effect transistor;

a gate pad electrically connected to a second end of said gate electrode strip line; and

a Faraday shield layer extending between both said gate electrode strip line and said gate pad and a drain of said field effect transistor so that said gate electrode strip line and said gate pad are capacitively decoupled from the drain.

42. The device of claim 41, wherein said Faraday shield layer is electrically connected to a source of said field effect transistor.

43. A semiconductor switching device, comprising:

a semiconductor substrate having a first surface thereon and a drift region of first conductivity type therein;

a quad arrangement of trenches that extend into the first surface of said semiconductor substrate and define a drift region mesa therebetween;

a base region of second conductivity type that extends into the drift region and forms a first P-N rectifying junction therewith;

a source region of first conductivity type that extends into the base region and forms a second P-N rectifying junction therewith;

a quad arrangement of insulated electrodes in said quad arrangement of trenches;

an insulated gate on the drift region mesa; and

a source electrode that extends on the first surface and is electrically connected to said source and base regions and to said quad arrangement of insulated electrodes.

44. The device of claim 43, wherein said quad arrangement of trenches includes a first pair of trenches at a front of the device and a second pair of trenches at a rear of the device, when the device is viewed in transverse cross-section.

45. The device of claim 44, wherein said source region extends along the first surface in a lengthwise direction from the front to the rear of the device without interruption by said base region.

46. The device of claim 45, wherein said base region extends along the first surface in the lengthwise direction from a sidewall of a trench in the first pair to a sidewall of an opposing trench in the second pair.

47. The device of claim 46, wherein said source electrode ohmically contacts said source region and said base region along the first surface.

48. The device of claim 44, wherein a first distance between the first pair of trenches and the second pair of trenches equals a width of the drift region mesa as measured between the first pair of trenches.

49. The device of claim 48, wherein said source region extends along the first surface in a lengthwise direction from the front to the rear of the device without interruption by said base region.

50. The device of claim 49, wherein said base region extends along the first surface in the lengthwise direction from a sidewall of a trench in the first pair to a sidewall of an opposing trench in the second pair.

51. The device of claim 50, wherein said source electrode ohmically contacts said source region and said base region along the first surface.

52. A semiconductor switching device, comprising:

a semiconductor substrate having a first surface thereon and a drift region of first conductivity type therein;

a quad arrangement of trenches that extend into the first surface of said semiconductor substrate and define a drift region mesa therebetween;

a base region of second conductivity type that extends into the drift region and forms a first P-N rectifying junction therewith;

a source region of first conductivity type that extends into the base region and forms a second P-N rectifying junction therewith;

a quad arrangement of insulated electrodes in said quad arrangement of trenches;

an insulated gate electrode on the first surface;

a Faraday shield layer that extends on the first surface and surrounds said quad arrangement of trenches;

a source electrode that extends on the first surface and is electrically connected to said source and base regions, said quad arrangement of insulated electrodes and said Faraday shield layer.

53. The device of claim 52, further comprising:

a gate electrode strip line on said Faraday shield layer; and

an intermediate electrically insulating layer extending between said Faraday shield layer and said gate electrode strip line.

54. The device of claim 53, wherein said intermediate electrically insulating layer provides electrostatic discharge protection to the device.

55. A packaged power device, comprising:

an electrically conductive flange having a slot therein;

an electrically conductive substrate mounted within the slot;

a dielectric layer on said electrically conductive substrate;

a gate electrode strip line that is patterned on said dielectric layer and extends opposite the electrically conductive substrate; and

a vertical power MOSFET having a source electrically coupled and mounted to a first portion of said flange located outside the slot and a gate electrode electrically coupled and mounted to a first end of said gate electrode strip line.

56. The device of claim 55, further comprising:

a drain terminal mounted to said flange and electrically coupled to a drain of said vertical power device; and

a gate terminal mounted to said flange and electrically coupled to said gate electrode strip line.

57. The device of claim 56, further comprising a gate metal strap that electrically connects said gate terminal to a second end of said gate electrode strip line.

58. The device of claim 55, wherein the source of said vertical power MOSFET is electrically connected to the first portion of the flange by a first solder bond;

and wherein the gate electrode is electrically connected to the first end of said gate electrode strip line by a second solder bond.

59. The device of claim 55, wherein said electrically conductive substrate comprises a semiconductor substrate that is electrically connected to said flange.

60. The device of claim 59, further comprising a polysilicon capacitor electrode that is electrically connected to said gate electrode strip line.

61. The device of claim 60, wherein said polysilicon capacitor electrode, said dielectric layer and said semiconductor substrate collectively form a MOS capacitor.

62. A packaged power transistor, comprising:

an electrically conductive flange having a slot therein;

a ceramic substrate mounted within the slot;

a gate electrode strip line that is patterned on said ceramic substrate and extends opposite a bottom of the slot; and

a vertical power MOSFET having a source electrically coupled and mounted to a first portion of said flange located outside the slot and a gate electrode electrically coupled and mounted to a first end of said gate electrode strip line.

63. A packaged power transistor device, comprising:

an electrically conductive flange having a slot therein;

an integrated circuit substrate mounted to a bottom of the slot, said integrated circuit substrate comprising a semiconductor layer that is electrically coupled to said flange, a dielectric layer on the semiconductor layer and a gate interconnect on the dielectric layer, said gate interconnect comprising a gate electrode strip line or a gate metal strap; and

a vertical power MOSFET having a source electrically coupled and mounted to a first portion of said flange located outside the slot and a gate electrode electrically coupled and mounted to the gate interconnect.

64. A power device, comprising:

an electrically conductive plate;

a ceramic insulating layer on a surface of said electrically conductive plate;

a gate electrode strip line extending on said ceramic insulating layer and opposite said electrically conductive plate; and

a vertical power MOSFET having a source electrode electrically coupled to said electrically conductive plate and a gate electrode electrically coupled to an end of said gate electrode strip line.

65. The device of claim 64, wherein said source electrode is electrically coupled to said electrically conductive plate by a first solder bond;

and wherein said gate electrode is electrically coupled to an end of said gate electrode strip line by a second solder bond.

66. The device of claim 64, wherein a width of said gate electrode strip line is less than about 0.2 times a width of said ceramic insulating layer when viewed in transverse cross-section.

67. The device of claim 65, wherein a thickness of the first solder bond is greater than a thickness of the second solder bond.

70. The device of claim 69, wherein said insulated gate electrode extends opposite said first and second base regions and the drift region;

and wherein said insulated gate electrode is patterned so that during forward on-state conduction, majority carriers provided by said first and second source regions flow across said first and second base regions in a direction parallel to said first and second stripe-shaped trenches.

68. A power device, comprising:

a device package comprising gate and drain terminals and an electrically conductive flange that operates as a source terminal;

an electrically conductive plate mounted to the electrically conductive flange;

a ceramic insulating layer on a surface of said electrically conductive plate;

a gate electrode strip line extending on said ceramic insulating layer and opposite said electrically conductive plate;

a vertical power MOSFET having a source electrode electrically coupled to said electrically conductive plate and a gate electrode electrically coupled to a first end of said gate electrode strip line;

a first electrical connector mounted to the drain terminal of said device package and a drain electrode of said vertical power MOSFET; and

a second electrical connector mounted to the gate terminal of said device package and a second end of said gate electrode strip line.

69. A vertical power device, comprising:

a semiconductor substrate having a drift region of first conductivity type therein extending adjacent a first face thereof;

first and second stripe-shaped trenches that extend in parallel and in a first direction across said semiconductor substrate;

first and second insulated electrodes in the first and second stripe-shaped trenches, respectively;

first and second base regions of second conductivity type that each extend from a sidewall of said first stripe-shaped trench to an opposing sidewall of said second stripe-shaped trench and define a respective P-N junction with the drift region;

first and second source regions of first conductivity type in said first and second base regions, respectively;

a source electrode that extends on the first face and is electrically connected to said first and second insulated electrodes and to said first and second source regions; and

an insulated gate electrode that extends in a second direction across the first face of said semiconductor substrate that is orthogonal to the first direction.

71. A UMOSFET, comprising:

a semiconductor substrate having a drift region of first conductivity type therein;

a first stripe-shaped trench in said semiconductor substrate;

an insulated gate electrode in said first stripe-shaped trench;

a second stripe-shaped trench that extends in said semiconductor substrate in a direction parallel to said first stripe-shaped trench;

an insulated source electrode in said second stripe-shaped trench;

a base region of second conductivity type that extends in the drift region and between opposing sidewalls of said first and second stripe-shaped trenches;

a source region of first conductivity type in said base region; and

a source electrode that extends on said semiconductor substrate and is electrically connected to said source region and to said insulated source electrode.

72. The UMOSFET of claim 71, wherein a depth of said second stripe-shaped trench is greater than a depth of said first stripe-shaped trench.

73. The UMOSFET of claim 72, further comprising a third stripe-shaped trench that extends in said semiconductor substrate in a direction parallel to said second stripe-shaped trench;

wherein said first stripe-shaped trench extends between said second and third stripe-shaped trenches; and

wherein a depth of said third stripe-shaped trench equals the depth of the second stripe-shaped trench.

74. A UMOSFET, comprising:

a semiconductor substrate having a drift region of first conductivity type therein;

first and second trenches that extend in said semiconductor substrate and define a drift region mesa therebetween;

first and second insulated source electrodes in said first and second trenches, respectively; and

a UMOSFET comprising a third trench that is shallower than said first and second trenches, in the drift region mesa.

75. The UMOSFET of claim 74, further comprising a first base shielding region of second conductivity type that forms a non-rectifying junction with a base region of said UMOSFET and a rectifying junction with the drift region and extends adjacent a first sidewall of said first trench.

76. The UMOSFET of claim 75, wherein said first base shielding region is self-aligned with the first sidewall of said first trench.

77. The UMOSFET of claim 74, further comprising a transition region of first conductivity type that forms a rectifying junction with a base region of said UMOSFET and a non-rectifying junction with the drift region.

78. The UMOSFET of claim 75, further comprising a transition region of first conductivity type that forms a rectifying junction with a base region of said UMOSFET and a non-rectifying junction with the drift region.

79. The UMOSFET of claim 76, further comprising a transition region of first conductivity type that forms a rectifying junction with a base region of said UMOSFET and a non-rectifying junction with the drift region.

80. A method of forming a vertical power device, comprising the steps of:

forming first and second deep trenches in a semiconductor substrate having a drift region of first conductivity type therein that extends into a mesa defined between first and second opposing sidewalls of the first and second deep trenches, respectively;

forming a UMOSFET in the mesa; and

forming first and second base shielding regions of second conductivity type that extend into the mesa and are self-aligned with the first and second opposing sidewalls.

81. The method of claim 80, further comprising the step of forming a transition region of first conductivity type that extends between the drift region and a base region of second conductivity type within the UMOSFET.

82. A method of forming a vertical MOSFET, comprising the steps of:

implanting base region dopants of second conductivity type into an active portion of a semiconductor substrate having a drift region of first conductivity type therein;

forming a first mask having openings therein on the active portion of the semiconductor substrate;

implanting shielding region dopants of second conductivity type into the active portion of the substrate, using the first mask as an implant mask;

driving-in the implanted base and shielding region dopants to define a base region and a plurality of base shielding regions that extend laterally underneath the first mask and vertically through the base region and into the drift region;

etching first and second deep trenches into the semiconductor substrate to define a drift region mesa therebetween, using the first mask as an etching mask;

forming first and second insulated source electrodes in the first and second trenches, respectively;

implanting source region dopants of first conductivity type into the drift region mesa;

driving-in the implanted source region dopants to define a source region in the base region;

forming a shallow trench that extends in the drift region mesa and has a sidewall extending adjacent the base and source regions;

forming an insulated gate electrode in the shallow trench; and

forming a source electrode that electrically connects the first and second insulated source electrodes, the source region and the base region together.

83. A method of forming a vertical power device, comprising the steps of:

forming first and second deep trenches in a semiconductor substrate having a drift region of first conductivity type therein that extends into a mesa defined between first and second opposing sidewalls of the first and second deep trenches, respectively; and

forming a UMOSFET in the mesa.