Optimized digital regulation of switching power supply

• US 20020057080A1
• Filed: 10/03/2001
• Published: 05/16/2002
• Est. Priority Date: 06/02/2000
• Status: Abandoned Application

• Current Assignee: Dialog Semiconductor Incorporated (Renesas Electronics Corporation)
• Original Assignee: iWatt, Inc. (Renesas Electronics Corporation)
• Inventors: Muegge, Mark, Wong, Dickson T., Geber, Charles R., Telefus, Mark D.
• Application Number:
  US09/970,849
• Publication Number:
  US 20020057080A1
• Time in Patent Office: Days
• US Class Current: 323/283
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 1/0041 Control circuits in which a clock signal is selectively enabled or disabled
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H02M 3/33515 with digital control
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A digitally controlled, transformer-coupled switching power supply for conversion of power between a source and a load includes a power switch that, when coupled to the source and cycled ON and OFF by a controller, supplies a pulse of power to the load. Control circuitry for the power converter includes a pulse generator for generating switch activation pulses to cycle the power switch, each switch activation pulse produced by the pulse generator defining a new switching cycle. A pulse rate controller is coupled to the pulse generator for regulating an output voltage at the load by selectively allowing, on a pulse by pulse basis, switch activation pulses to cycle the power switch. A pulse optimizer is coupled to the pulse generator, the pulse optimizer controlling one or both of (1) when the pulse generator generates a respective switch activation pulse to initiate a new switching cycle in order to minimize converter losses by effecting zero-voltage switching across the transformer, and (2) the width of the switch activation pulses in order to maintain constant primary side peak current, regardless of variations in input line voltage.

Claims

1. A controller for controlling a power supply for conversion of power between a source and a load, the power supply including a power switch that, when coupled to the source and cycled ON and OFF, supplies a pulse of power to the load, the controller comprising:

pulse generation circuitry for generating switch activation pulses to cycle the power switch, each switch activation pulse produced by the pulse generator defining a new switching cycle; and

pulse optimization circuitry coupled to the pulse generation circuitry for controlling when a switch activation pulse is generated to initiate a switching cycle.

2. The controller of claim 1, wherein the pulse generation circuitry and the pulse optimization circuitry are implemented as a single circuit.

3. The controller of claim 1, wherein the pulse optimization circuitry causes a switch activation pulse to be generated to initiate a new switching cycle based on a primary side voltage condition.

4. The controller of claim 1, wherein the pulse optimization circuitry causes a switch activation pulse to be generated to initiate a new switching cycle when the primary side voltage is approximately zero.

5. The controller of claim 1, wherein the pulse optimization circuitry further controls a width of the switch activation pulses.

6. The controller of claim 5, wherein the pulse optimization circuitry determines the width of a switch activation pulse for a present switching cycle based on a primary side current during a previous switching cycle.

7. The controller of claim 5, wherein the pulse optimization circuitry determines the width of a switch activation pulse for a present switching cycle based on a power switch ON time needed to reach a primary side peak current during a previous switching cycle.

8. The controller of claim 7, the source having a variable input line voltage, wherein the primary side peak current is constant for all input voltages.

9. The controller of claim 7, the source having a variable input line voltage, wherein the primary side peak current varies in relation to the input voltage.

10. The controller of claim 9, wherein the primary side peak current has a first value for a first input voltage range, and a second value for a second input voltage range.

11. The controller of claim 1, further comprising pulse rate control circuitry coupled to the pulse generation circuitry for regulating an output voltage at the load by selectively allowing switch activation pulses to cycle the power switch.

12. The controller of claim 11, wherein the pulse generation circuitry, pulse optimization circuitry and pulse rate control circuitry are implemented as a single circuit.

13. The controller of claim 1, wherein the switch activation pulses include power pulses and sense pulses,

wherein the power switch, when cycled ON and OFF by a power pulse, supplies a substantial pulse of power to the load,

wherein the power switch, when cycled ON and OFF by a sense pulse, supplies an insubstantial pulse of power to the load, and

wherein the pulse optimization circuitry causes a power pulse or a sense pulse to be generated to initiate a new switching cycle based on a primary side voltage condition.

14. The controller of claim 13, wherein the pulse optimization circuitry causes a power pulse or a sense pulse to be generated to initiate a new switching cycle when the primary side voltage is approximately zero.

16. The controller of claim 15, wherein the pulse optimization circuitry is implemented in the respective first and second pulse generators.

17. The controller of claim 15, wherein the pulse optimization circuitry causes respective power and sense pulses to be generated to initiate a new switching cycle based on a primary side voltage condition.

18. The controller of claim 15, wherein the pulse optimization circuitry causes respective power and sense pulses to be generated to initiate a new switching cycle when the primary side voltage is approximately zero.

19. The controller of claim 15, wherein the pulse optimization circuitry further controls a width of the power pulses generated by the first pulse generator.

20. The controller of claim 19, wherein the pulse optimization circuitry determines a width of a power pulse for a present switching cycle based on a primary side current during a previous switching cycle.

21. The controller of claim 19, wherein the pulse optimization circuitry determines a width of a power pulse for a present switching cycle based on a power switch ON time needed to reach a primary side peak current during a previous switching cycle.

22. The controller of claim 21, the source having a variable input line voltage, wherein the primary side peak current is constant for all input voltages.

23. The controller of claim 21, the source having a variable input line voltage, wherein the primary side peak current varies in relation to the input voltage.

24. The controller of claim 23, the primary side peak current having a first value for a first input voltage range and a second value for a second input voltage range.

25. The controller of claim 15, further comprising pulse rate control circuitry coupled to the first and second pulse generators for regulating an output voltage at the load by selectively allowing, for each switching cycle, a power pulse, a sense pulse, or no pulse to cycle the power switch.

27. The power supply of claim 26, wherein the pulse generation circuitry and the pulse optimization circuitry are implemented as a single circuit.

28. The power supply of claim 26, wherein the pulse optimization circuitry causes a switch activation pulse to be generated to initiate a new switching cycle based on a primary side voltage condition.

29. The power supply of claim 26, wherein the pulse optimization circuitry determines a width of a switch activation pulse for a present switching cycle based on a power switch ON time needed to reach a primary side peak current during a previous switching cycle.

30. The power supply of claim 26, wherein the switch activation pulses include power pulses and sense pulses,

wherein the power switch, when cycled ON and OFF by a power pulse, supplies a substantial pulse of power to the load,

wherein the power switch, when cycled ON and OFF by a sense pulse, supplies an insubstantial pulse of power to the load, and

wherein the pulse optimization circuitry causes a power pulse or a sense pulse to be generated to initiate a new switching cycle based on a primary side voltage condition.

31. The power supply of claim 30, wherein the pulse optimization circuitry causes a power pulse or a sense pulse to be generated to initiate a new switching cycle when the primary side voltage is approximately zero.

32. The power supply of claim 26, further comprising pulse rate control circuitry coupled to the pulse generation circuitry for regulating an output voltage at the load by selectively allowing switch activation pulses to cycle the power switch.

15. A controller for controlling a power supply for conversion of power between a source and a load, the power supply including a power switch that, when coupled to the source and cycled ON and OFF, supplies a pulse of power to the load, the controller comprising:

a first pulse generator for generating switch activation power pulses for cycling the power switch, wherein the power switch, when cycled ON and OFF by a power pulse, supplies a substantial pulse of power to the load;

a second pulse generator for generating switch activation sense pulses for cycling the power switch, wherein the power switch, when cycled ON and OFF by a sense pulse, supplies a an insubstantial pulse of power to the load;

the first and second pulse generators generating respective power and sense pulses at a same frequency, the production of a respective pulse by the first and second pulse generators defining a new switching cycle; and

pulse optimization circuitry coupled to the first and second pulse generators, the pulse optimization circuitry controlling when the first and second pulse generators generate respective power and sense pulses to initiate a switching cycle.

26. A power supply for conversion of power between a source and a load, comprising:

a power switch that, when coupled to the source and cycled ON and OFF, supplies a pulse of power to the load;

pulse generation circuitry for generating switch activation pulses to cycle the power switch, each switch activation pulse produced by the pulse generator defining a new switching cycle; and

pulse optimization circuitry coupled to the pulse generation circuitry for controlling when a switch activation pulse is generated to initiate a switching cycle.

33. A power supply for controlling a power supply for conversion of power between a source and a load, comprising:

a power switch that, when coupled to the source and cycled ON and OFF, supplies a pulse of power to the load;

a first pulse generator for generating switch activation power pulses for cycling the power switch, wherein the power switch, when cycled ON and OFF by a power pulse, supplies a substantial pulse of power to the load;

a second pulse generator for generating switch activation sense pulses for cycling the power switch, wherein the power switch, when cycled ON and OFF by a sense pulse, supplies a an insubstantial pulse of power to the load;

the first and second pulse generators generating respective power and sense pulses at a same frequency, the production of a respective pulse by the first and second pulse generators defining a new switching cycle; and

pulse optimization circuitry coupled to the first and second pulse generators, the pulse optimization circuitry controlling when the first and second pulse generators generate respective power and sense pulses to initiate a switching cycle.

34. The power supply of claim 33, wherein the pulse optimization circuitry determines a width of a power pulse for a present switching cycle based on a power switch ON time needed to reach a primary side peak current during a previous switching cycle.