PLL circuit and optical communication reception apparatus
First Claim
1. A PLL circuit, comprising:
- an oscillator for generating an oscillation frequency signal having a variable oscillation frequency;
a phase detection circuit for comparing the phases of the oscillation frequency signal of said oscillator and an input signal with each other and outputting, based on a result of the comparison, a first phase control signal for advancing the phase of the oscillation frequency signal of said oscillator or a second phase control signal for delaying the phase of the oscillation frequency signal of said oscillator;
a signal generation circuit for generating first and second signals having different phases from each other based on the oscillation frequency signal of said oscillator; and
a frequency detection circuit for fetching the first and second signals generated by said signal generation circuit in synchronism with the input signal for each period of the input signal, logically operating the fetched signals and signals having been fetched in the immediately preceding period and outputting, based on a result of the arithmetic operation, a first frequency control signal for raising the frequency of the oscillation frequency signal of said oscillator or a second frequency control signal for lowering the frequency of the oscillation frequency signal of said oscillator.
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Abstract
The invention provides a PLL circuit wherein, even if the duty ratio of an input signal varies, stabilized PLL operation is achieved. The PLL circuit includes a phase detection circuit and a frequency detection circuit. The frequency detection circuit includes a pair of D-type flip-flops for sampling first and second clock signals having different phases from each other in synchronism with an input signal at each rising or falling changing point of the input signal for each period, and a control logic circuit for logically operating the signals sampled by the D-type flip-flops and the signals sampled successively subsequently by the D-type flip-flops. The control logic circuit generates an UP pulse signal or a DOWN pulse signal based on a result of the arithmetic operation.
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Citations
18 Claims
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1. A PLL circuit, comprising:
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an oscillator for generating an oscillation frequency signal having a variable oscillation frequency;
a phase detection circuit for comparing the phases of the oscillation frequency signal of said oscillator and an input signal with each other and outputting, based on a result of the comparison, a first phase control signal for advancing the phase of the oscillation frequency signal of said oscillator or a second phase control signal for delaying the phase of the oscillation frequency signal of said oscillator;
a signal generation circuit for generating first and second signals having different phases from each other based on the oscillation frequency signal of said oscillator; and
a frequency detection circuit for fetching the first and second signals generated by said signal generation circuit in synchronism with the input signal for each period of the input signal, logically operating the fetched signals and signals having been fetched in the immediately preceding period and outputting, based on a result of the arithmetic operation, a first frequency control signal for raising the frequency of the oscillation frequency signal of said oscillator or a second frequency control signal for lowering the frequency of the oscillation frequency signal of said oscillator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18)
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13. An optical communication reception apparatus, comprising:
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light reception means for receiving an optical signal, converting the optical signal into an electric signal and outputting the electric signal;
a PLL circuit for producing a clock signal synchronized with the output signal of said light reception means; and
a retiming circuit for retiming the output signal of said light reception means based on the clock signal produced by said PLL circuit;
said PLL circuit including an oscillator for generating an oscillation frequency signal having a variable oscillation frequency, a phase detection circuit for comparing the phases of the oscillation frequency signal of said oscillator and an input signal with each other and outputting, based on a result of the comparison, a first phase control signal for advancing the phase of the oscillation frequency signal of said oscillator or a second phase control signal for delaying the phase of the oscillation frequency signal of said oscillator, a signal generation circuit for generating first and second signals having different phases from each other based on the oscillation frequency signal of said oscillator, and a frequency detection circuit for fetching the first and second signals generated by said signal generation circuit in synchronism with the input signal for each period of the input signal, logically operating the fetched signals and signals having been fetched in the immediately preceding period and outputting, based on a result of the arithmetic operation, a first frequency control signal for raising the frequency of the oscillation frequency signal of said oscillator or a second frequency control signal for lowering the frequency of the oscillation frequency signal of said oscillator.
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Specification