Nonvolatile semiconductor memory device having reduced erase time and method of erasing data of the same

• US 20020057599A1
• Filed: 05/01/2001
• Published: 05/16/2002
• Est. Priority Date: 11/16/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Shimizu, Satoshi, Tomoeda, Mitsuhiro, Ohba, Atsushi, Miyawaki, Yoshikazu
• Granted Patent: US 6,515,908 B2
• Time in Patent Office: Days
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

Erasing is performed two times for narrowing a distribution width of threshold voltages of memory cells, and reducing the number of memory transistors to be subjected to over-erase verify. The erase verify voltage for the first erasing is set more strictly than the erase verify voltage for the second erasing. The erase pulses for the second erasing can be reduced in number, and the erasing time can be further reduced.

Claims

1. A nonvolatile semiconductor memory device comprising:

a memory block including a plurality of nonvolatile memory transistors arranged in rows and columns;

a plurality of word lines selecting the rows of said memory transistors, respectively;

a plurality of bit lines provided corresponding to the columns of said memory transistors;

a potential generating portion generating potentials to be applied to said plurality of word lines, said plurality of bit lines, and substrates and sources of said plurality of memory transistors; and

a program/erase control portion controlling said potential generating portion to erase data in said memory block,

said program/erase control portion including

a first setting portion collectively and repetitively applying a first erase pulse to said plurality of memory transistors to set said plurality of memory transistors to a first erased state,

a second setting portion setting said plurality of memory transistors to a second erased state providing the over-erased memory transistors smaller in number than the over-erased memory transistors in said first erased state, and

a recovery control portion selectively performing the recovery on said over-erased memory transistors when said second erased state is verified;

each of said memory transistors is an MOS transistor having a floating gate;

said first erased state is achieved when said plurality of memory transistors have the threshold voltages equal to or smaller than a first value; and

said second erased state is achieved when said plurality of memory transistors have the threshold voltages equal to or smaller than a second value.

2. The nonvolatile semiconductor memory device according to claim 1, wherein

said second setting portion includes

a first pulse control portion collectively applying a first program pulse to said plurality of memory transistors in said first erased state, and

a second pulse control portion repeating an operation of collectively applying a second erase pulse to said plurality of memory transistors already supplied with said first program pulse until said plurality of memory transistors attain said second erased state.

3. The nonvolatile semiconductor memory device according to claim 1, wherein

said second setting portion includes

a first pulse control portion collectively applying a first program pulse to said plurality of memory transistors in said first erased state until said plurality of memory transistors attain a predetermined recovered state, and

a second pulse control portion repeating an operation of collectively applying a second erase pulse to said plurality of memory transistors in said predetermined recovered state until said plurality of memory transistors attain said second erased state.

4. The nonvolatile semiconductor memory device according to claim 3, wherein

said predetermined recovered state refers to a state in which the number of said memory transistors in said memory block having the threshold voltages smaller than said first value is smaller than a predetermined number.

5. The nonvolatile semiconductor memory device according to claim 1, wherein

said second setting portion includes

a first pulse applying portion for collectively applying a first program pulse to said plurality of memory transistors in said first erased state, and thereafter repeating an operation of collectively applying a second erase pulse to said plurality of memory transistors until said plurality of memory transistors attain said second erased state.

6. The nonvolatile semiconductor memory device according to claim 1, further comprising

a pretreatment portion collectively applying a preliminary program pulse for performing preliminary programming before erasure to said plurality of memory transistors prior to setting said plurality of memory transistors to said first erased state.

7. The nonvolatile semiconductor memory device according to claim 6, wherein

an amount of shift of the threshold voltage of said memory transistor caused by application of said program pulse is smaller than an amount of shift of the threshold voltage of said memory transistor caused by application of said preliminary program pulse.

8. A method of erasing data of a nonvolatile semiconductor memory device provided with a memory block including a plurality of nonvolatile memory transistors arranged in rows and columns, a plurality of word lines for selecting the rows of said memory transistors, respectively, a plurality of bit lines provided corresponding to the columns of said memory transistors, a potential generating portion for generating potentials to be applied to said plurality of word lines, said plurality of bit lines, and substrates and sources of said plurality of memory transistors, and a program/erase control portion for controlling said potential generating portion to erase data in said memory block, comprising the steps of:

collectively and repetitively applying a first erase pulse to said plurality of memory transistors to set said plurality of memory transistors to a first erased state; and

setting said plurality of memory transistors to a second erased state providing the over-erased memory transistors smaller in number than the over-erased memory transistors in said first erased state; and

performing selectively the recovery on said over-erased memory transistors when said second erased state is verified, wherein

each of said memory transistors is an MOS transistor having a floating gate,

said first erased state is achieved when said plurality of memory transistors have the threshold voltages equal to or smaller than a first value, and

said second erased state is achieved when said plurality of memory transistors have the threshold voltages equal to or smaller than a second value.

9. The method of erasing data of the nonvolatile semiconductor memory device according to claim 8, wherein

said step of setting said plurality of memory transistors to said second erased state includes the steps of

collectively applying a first program pulse to said plurality of memory transistors in said first erased state, and

repeating an operation of collectively applying a second erase pulse to said plurality of memory transistors already supplied with said first program pulse until said plurality of memory transistors attain said second erased state.

10. The method of erasing data of the nonvolatile semiconductor memory device according to claim 8, wherein

said step of setting said plurality of memory transistors to said second erased state includes the steps of

collectively applying a first program pulse to said plurality of memory transistors in said first erased state until said plurality of memory transistors attain a predetermined recovered state, and

repeating an operation of collectively applying a second erase pulse to said plurality of memory transistors in said predetermined recovered state until said plurality of memory transistors attain said second erased state.

11. The method of erasing data of the nonvolatile semiconductor memory device according to claim 10, wherein

said predetermined recovered state refers to a state in which the number of said memory transistors in said memory block having the threshold voltages smaller than said first value is smaller than a predetermined number.

12. The method of erasing data of the nonvolatile semiconductor memory device according to claim 8, wherein

said step of setting said plurality of memory transistors to said second erased state includes the step of

collectively applying a first program pulse to said plurality of memory transistors in said first erased state, and thereafter repeating an operation of collectively applying a second erase pulse to said plurality of memory transistors until said plurality of memory transistors attain said second erased state.

13. The method of erasing data of the nonvolatile semiconductor memory device according to claim 8, further comprising the step of

collectively applying a preliminary program pulse for performing preliminary programming before erasure to said plurality of memory transistors prior to said step of setting to said first erased state.

14. The method of erasing data of the nonvolatile semiconductor memory device according to claim 13, wherein

an amount of shift of the threshold voltage of said memory transistor caused by application of said program pulse is smaller than an amount of shift of the threshold voltage of said memory transistor caused by application of said preliminary program pulse.