Integrated Circuit Devices Having Contact And Container Structures

• US 20020058380A1
• Filed: 12/31/2001
• Published: 05/16/2002
• Est. Priority Date: 08/31/2000
• Status: Active Grant

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: John K. Zahurak, Kunal R. Parekh
• Inventors: Parekh, Kunal R., Zahurak, John K.
• Granted Patent: US 6,617,635 B2
• Time in Patent Office: Days
• US Class Current: 438/253
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/312 with a bit line higher than the capacitor

Abstract

Methods for forming contact structures and container structures, as well as integrated circuits that can be formed by employing those methods are provided. The integrated circuitry formed by the methods of the present invention provide capacitors in containers having sufficiently high storage capacitance for advanced integrated circuit devices. In addition the methods for forming such container capacitors facilitate the formation of contacts structures and provided for the formation of local interconnect structures and electrical contact to each of the structures formed.

Claims

1. A method for forming contact structures and container structures, comprising:

providing a semiconductor substrate comprising a first insulative layer formed over the substrate, a second insulative layer formed over the first insulative layer, the first insulative layer having a plurality of first contact structures formed therein, the first contact structures having a first conductivity type;

forming a third insulative layer over the second insulative layer;

prior to forming the third insulative layer, separately forming a second contact structure within the second insulative layer and the first insulative layer, the second contact structure having a second conductivity type, different than the first conductivity type; and

prior to forming the third insulative layer, separately forming a container structure overlying one of the plurality of first contact structures, the container structure electrically contacting the first contact structure.

2. The method of claim 1, wherein providing the semiconductor substrate comprises providing the substrate having a memory array region, an N-peripheral region and a P-peripheral region.

3. The method of claim 2, wherein the plurality of first contact structures comprise memory array contact structures for electrically contacting portions of the memory array region and a P-peripheral contact structure for electrically contacting a portion of the P-peripheral region.

4. The method of claim 3, wherein forming the container structure comprises forming the container structure overlying and electrically contacting one of the memory array contact structures.

5. The method of claim 2, wherein forming the second contact structure comprises forming a contact structure electrically contacting a portion of the N-peripheral region.

6. The method of claim 1, wherein the first contact structures comprise N-type polysilicon and the second contact structure comprises P-type polysilicon.

7. The method of claim 1 wherein the first insulative layer comprises a borophosphosilicate glass (BPSG) material of a first thickness and the second insulative layer comprises a BPSG material of a second thickness, the second thickness being at least twice the first thickness.

8. The method of claim 7 further comprising forming a layer disposed between the first insulative layer and the second insulative layer, such layer comprising a material selectively etchable with respect to the second insulative layer.

9. The method of claim 1 further comprising forming a layer of capacitor structure material within each container, the capacitor structure material having inwardly facing outer surfaces and a space therebetween.

10. The method of claim 9 wherein forming the layer of capacitor structure material comprises forming a layer of hemispherical grained (HSG) polysilicon and a layer of dielectric material overlying the HSG layer, the dielectric layer having the inwardly facing outer surfaces.

11. The method of claim 10 wherein forming the layer of dielectric material comprises forming a layer of material comprising silicon nitride.

12. The method of claim 9, further comprising forming a plurality of third contact structures within the second insulative layer, each third contact structure electrically contacting one first contact structure not contacting a container structure.

13. The method of claim 12, further comprising forming a fourth contact structure within the second insulative layer and a portion of the first insulative layer, the fourth contact structure electrically contacting an N-peripheral region gate structure.

14. The method of claim 13, wherein the fourth contact structure is formed essentially simultaneously with the forming of the plurality of third contact structures.

15. The method of claim 9, further comprising forming a capacitor plate material, such material contacting the inwardly facing outer surface of the capacitor structure material and filling the space therebetween.

16. The method of claim 15, wherein the capacitor plate material comprises a polysilicon material.

17. The method of claim 15 wherein the capacitor plate material comprises a material selected from the group of materials consisting of a polysilicon material, platinum, ruthenium, rhodium, iridium, ruthenium oxide and iridium oxide.

18. The method of claim 15 wherein the capacitor plate material further comprises a polysilicon material.

19. The method of claim 18 further comprising:

forming a layer of capacitor plate material over an upper surface of the second insulative layer; and

patterning the layer of capacitor plate material to form local interconnect structures.

20. The method of claim 18 further comprising forming a third insulative layer over the second insulative layer and local interconnects.

21. The method of claim 20 further comprising simultaneously forming a plurality of contact structures disposed, in their entirety, within the third insulative layer, each of such contact structures electrically contacting an underlying contact structure or local interconnect.

22. The method of claim 21, wherein forming the plurality of contact structures disposed, in their entirety, within the third insulative layer, comprises depositing a layer of tungsten comprising material to fill at least a portion of such contact structures.

24. The method of claim 23, wherein the second thickness is at least twice the first thickness.

25. The method of claim 23, further comprising etching to form a plurality of container structures within the second insulative layer, the etching separate from the etching to form the second opening.

26. The method of claim 25 further comprising:

etching to form a plurality of third openings within the second insulative layer; and

prior to etching to form the plurality of third openings, forming capacitor structure material disposed within the container structure, the capacitor structure material having outwardly facing inner surfaces with a space formed therebetween; and

forming capacitor plate material wherein the capacitor plate material is disposed to essentially simultaneously fill each of the plurality of third openings and each of the plurality of containers, such forming of capacitor plate material forming a container capacitor and a local interconnects over the second insulative layer.

27. The method of claim 26, wherein forming capacitor plate material comprises forming a material selected from a group of materials consisting of a doped polysilicon material, platinum, ruthenium, rhodium, iridium, ruthenium oxide and iridium oxide.

28. The method of claim 26, further comprising patterning the layer of capacitor plate material to define a plurality of local interconnect structures, each interconnect structure contiguous with a filled contact hole and/or a filled capacitor container.

29. The method of claim 28 further comprising calculating the second thickness based on a desired capacitance of the container capacitor.

30. The method of claim 26, further comprising forming a third insulative layer disposed overlying the second insulative layer and plurality of local interconnects, the third insulative layer having a thickness of at least about 1000 nm.

31. The method of claim 30, further comprising forming a plurality of contact structures, each contact structure formed in its entirety within the third insulative layer.

23. A method of forming an integrated circuit comprising:

providing a semiconductor substrate comprising a memory array region, an N-peripheral region and a P-peripheral region, a first insulative layer, having a first thickness, formed over such regions, said first insulative layer having a plurality of first contact structures formed therein, each first contact structure overlying either the memory array region or the P-peripheral region, the first contact structures comprising a conductive material of a first conductivity type;

forming a second insulative layer having a second thickness greater than the first thickness;

etching to form second opening through the second insulative layer and the first insulative layer, the second opening exposing a portion of the N-peripheral region; and

filling the second opening with a conductive material of a second conductivity type, opposite the first type.

32. A DRAM comprising:

a semiconductor substrate comprising a first insulative layer over the substrate and a second insulative layer over the first insulative layer, the first insulative layer having a plurality of first contact structures formed in their entirety therein, the first contact structures having a first conductivity type;

a plurality of second interconnect structures formed in their entirety within the second insulative layer;

a capacitor container structure, the container formed in its entirety with the second insulative layer;

a third contact structure formed in its entirety within the first insulative layer and the second insulative layer, the third contact structure having a second conductivity type opposite the first type;

a plurality of local interconnect structures overlying the second insulative layer; and

a third insulative layer overlying the second insulative layer and the plurality of local interconnects, the third insulative layer having a plurality of fourth contact structures formed in their entirety therein, each fourth contact structure contacting one of the local interconnect structures, one of the second interconnect structures or the third interconnect structure.

33. The DRAM of claim 32, wherein the first insulative layer has a first thickness and the second insulative layer has a second thickness, the second thickness at least twice the first thickness.

34. The DRAM of claim 32, wherein the capacitor container structure, the plurality of second interconnect structures and the plurality of local interconnect comprise a capacitor plate material.

35. The DRAM of claim 34, wherein the capacitor plate material comprises a material selected from the group consisting of a polysilicon material, platinum, ruthenium, rhodium, iridium, ruthenium oxide and iridium oxide.

36. The DRAM of claim 34, wherein the capacitor plate material comprises a doped polysilicon material.

37. The DRAM of claim 34, wherein the fourth contact structures comprise a tungsten comprising material.

38. The DRAM of claim 32, the substrate further comprising a memory array portion, an N-peripheral portion and a P-peripheral portion.

39. The DRAM of claim 38, wherein memory array portion comprises an array of gate structures, each gate structure operatively coupled to adjacent source and drain regions and the N-peripheral and P-peripheral portions each comprise at least one contact enhancement region forming in the substrate and a gate structure formed over the substrate.

40. The DRAM of claim 39 wherein the third contact structure is electrically coupled to the contact enhancement region of the P-peripheral region.

41. The DRAM of claim 32, wherein the third insulative layer has a thickness of at least about 1000 nm.