Full-speed bist controller for testing embedded synchronous memories

• US 20020059543A1
• Filed: 03/05/2001
• Published: 05/16/2002
• Est. Priority Date: 11/13/2000
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Cheng, Wu-Tung, Kebichi, Omar, Hill, Christopher John
• Granted Patent: US 6,829,728 B2
• Time in Patent Office: Days
• US Class Current: 714/30
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

A test circuit is disclosed for testing embedded synchronous memories. A BIST controller is used to address the memory and provide reference data that is compared to the memory output. Pipeline registers are used to allow the BIST controller to perform reads and/or writes during every clock cycle. In one aspect, the BIST controller includes a reference data circuit that stores or generates data for comparison to the memory output. A pipeline register is positioned before the reference data circuit or between the reference data circuit and compare circuitry. Additional pipeline registers may be positioned between a compare capture circuit and the compare circuitry. The pipeline registers free the BIST controller from having to wait for a read to complete before starting the next read or write. To reduce the number of pipeline registers needed, a negative-edge BIST controller can be used with a positive-edge memory or vice versa.

Claims

1. A circuit for testing embedded synchronous memory in an integrated circuit, comprising:

a memory having a plurality of memory words for storing data, the memory having an address port used to identify a memory word during a read or write operation of the memory, a data port that receives data to be written to the memory word during a write operation, and an output port to provide the memory word during a read operation;

a BIST controller coupled to the memory, the BIST controller having a BIST address port coupled to the address port on the memory, a BIST data port coupled to the data port on the memory, and a finite state machine that controls the state of the BIST controller;

compare circuitry coupled to the memory output port; and

at least one pipeline register coupled between the compare circuitry and the finite state machine that delays data to the compare circuitry.

2. The circuit of claim 1, further including a reference data circuit positioned between the finite state machine and the compare circuitry, the reference data circuit used to either store or generate an expected data value to be provided to the compare circuitry.

3. The circuit of claim 2, wherein the at least one pipeline register is positioned between the finite state machine and the reference data circuit.

4. The circuit of claim 2, wherein the at least one pipeline register is positioned between the reference data circuit and the compare circuitry.

5. The circuit of claim 1, further including a clock coupled to BIST controller, the finite state machine changing state in response to the clock, wherein the delay causes data to be received by the compare circuitry at least one clock cycle after the finite state machine state for generation of the data.

6. The circuit of claim 1, further including a clock coupled to the BIST controller and the memory for synchronization of the testing of memory.

7. The circuit of claim 1, wherein the BIST controller includes a compare capture circuit that controls the compare circuitry.

8. The circuit of claim 1, wherein the compare circuitry performs a bit-by-bit comparison of the memory word to data provided by the reference data circuit and provides an output indicating whether there is a match between the memory word and the data.

9. The circuit of claim 1, further including a clock coupled to the BIST controller and the memory, wherein the BIST controller performs consecutive read operations on the memory every clock cycle while testing the memory.

10. The circuit of claim 1, further including a clock coupled to the BIST controller and the memory wherein the BIST controller writes data to the memory on consecutive clock cycles of the memory to test the memory.

11. The circuit of claim 1, wherein the BIST controller includes a compare capture circuit and the at least one pipeline register is located between the compare capture circuit and the compare circuitry.

12. The circuit of claim 1, wherein the memory is a negative-edge memory that reads or writes on a falling edge of a clock cycle.

13. The circuit of claim 1, wherein the BIST controller is a negative-edge BIST controller that loads the address register on a falling edge of a clock cycle.

14. The circuit of claim 1, wherein the reference data circuit is coupled to a reference data selector for selecting one of a plurality of constants to pass to the compare circuitry.

15. The circuit of claim 14, wherein the reference data selector is the at least one pipeline register.

17. The method of claim 16, wherein the pipelining is accomplished by positioning at least one pipeline register between a finite state machine and the compare circuitry.

18. The method of claim 17, wherein the pipelining is accomplished by positioning the pipeline register within the BIST controller.

19. The method of claim 16, wherein the pipelining includes positioning a pipeline register to store the expected data value from a BIST controller and providing the expected data value to the compare circuitry one clock cycle after the BIST controller generates the expected data value.

20. The method of claim 16, wherein the pipelining includes providing at least one pipeline register between a compare capture circuit within the BIST controller and the compare circuitry.

21. The method of claim 16, wherein the pipelining includes two pipeline registers positioned in series between the compare capture circuit and the compare circuitry.

22. The method of claim 16, further including clocking the memory on an opposite edge than the BIST controller is clocked.

25. The method of claim 24 wherein (a)-(e) are repeated for N clock cycles, where N is an integer value.

26. The method of claim 24 further including providing a clock that clocks over N clock cycles and wherein the first clock cycle is an arbitrary clock cycle selected from one of the N clock cycles.

27. The method of claim 24 further including pipelining data from a BIST controller that provides the expected data value to a compare circuit performing the comparing.

28. The method of claim 24 further including using a negative-edge BIST controller that provides the expected data value and a positive-edge memory.

29. The method of claim 24 further including using a positive-edge BIST controller that provides the expected data value and a negative-edge memory.

30. The method of claim 24 wherein a BIST controller and a memory are synchronized by coupling both to a same clock.

16. A method for testing embedded synchronous memory in an integrated circuit, the method comprising:

generating an expected data value;

pipelining the generated expected data value to delay the expected data value at least one clock cycle;

reading an actual data value from the memory; and

comparing the actual data value to the pipelined expected data value using compare circuitry.

23. A circuit used in testing embedded memory in an integrated circuit, comprising providing pipelined registers between a finite state machine and compare circuitry so that the circuit can read data from memory on consecutive clock cycles and compare the read data to an expected data value during the same clock cycle as the reads, and wherein the circuit provides the results of consecutive reads on every clock cycle.

24. A method for testing embedded memory, comprising:

(a) during a first clock cycle, setting up an address register for a first read of memory;

(b) during a second clock cycle, completing the first read and comparing the data read to an expected data value;

(c) during the second clock cycle, setting up the address register for a second read or a write;

(d) during a third clock cycle, providing an output for the first read indicating whether the first read past or failed based on whether the data read matched the expected data value; and

(e) during the third clock cycle, completing the second read or the write.

31. A method for testing embedded synchronous memory in an integrated circuit, the method comprising:

(a) selectively configuring the integrated circuit into a test mode for testing the memory;

(b) using a BIST controller, loading an address of the memory location to be tested;

(c) using the BIST controller, generating an expected data value that represents the correct data associated with the memory address;

(d) using the BIST controller, providing control signals to or loading a compare capture circuit used to control compare circuitry;

(e) reading the actual data value from the memory, the data value stored in memory at the memory address generated by the BIST controller;

(f) comparing the actual data value from the memory with the expected data value from the BIST controller; and

(g) pipelining at least the compare capture circuit so that the BIST controller can perform consecutive reads and compares every clock cycle of the memory.