Minimally- patterned, thin-film semiconductor devices for display applications

• US 20020060321A1
• Filed: 07/12/2001
• Published: 05/23/2002
• Est. Priority Date: 07/14/2000
• Status: Abandoned Application

• Current Assignee: E Ink Corporation (E Ink Holdings Incorporated)
• Original Assignee: E Ink Corporation (E Ink Holdings Incorporated)
• Inventors: Denis, Kevin, Drzaic, Paul S., Chen, Yu, Kazlas, Peter T.
• Application Number:
  US09/904,435
• Publication Number:
  US 20020060321A1
• Time in Patent Office: Days
• US Class Current: 257/66
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

A thin-film transistor array comprises at least first and second transistors. Each of the first and second transistors include a shared silicon layer, i.e., an active layer, having a thickness less than approximately 40 nm. The shared silicon layer extends continuously between the first and second transistors. The silicon layer may consist of unpatterned silicon. Heavily doped material may not be required at metal-silicon contact interfaces.

Claims

1. A thin-film transistor array comprising at least first and second transistors, each of the first and second transistors comprising:

a shared silicon layer having a thickness less than 40 nm and extending continuously between the first and second transistors;

a source electrode in direct contact with the silicon layer;

a drain electrode spaced from the source electrode and in direct contact with the silicon layer; and

a gate electrode disposed adjacent to the silicon layer.

2. The thin-film transistor array of claim 1 wherein the silicon layer consists of unpatterned silicon.

3. The thin-film transistor array of claim 2 wherein the silicon layer consists of amorphous silicon.

4. The thin-film transistor array of claim 1 wherein the silicon layer is undoped.

5. The thin-film transistor array of claim 1 wherein the first transistor is a bottom gate transistor.

6. The thin-film transistor array of claim 1 wherein the first transistor is a top gate transistor.

7. The thin-film transistor array of claim 1, the first transistor further comprising a first pixel electrode of an electronic display, the first pixel electrode in communication with the source electrode of the first transistor, and the drain electrode of the first transistor is in communication with a first data line of the electronic display.

8. The thin-film transistor array of claim 7 wherein a distance between the first pixel electrode and the first data line is selected to provide an acceptable leakage current between the first pixel electrode and the first data line.

9. The thin-film transistor array of claim 7 wherein a distance between the first transistor and the second transistor is selected to provide an acceptable leakage current between the first data line and the second data line.

10. The thin-film transistor array of claim 9 wherein at least one of the first data line, the second data line, the first transistor and the first pixel electrode have a geometry selected to provide an acceptable leakage between the first data line and the second data line.

11. An electronic display comprising:

a display medium;

a first pixel electrode and a second pixel electrode provided adjacent to the display medium; and

a first thin-film transistor and a second thin-film transistor in respective electrical communication with the first pixel electrode and the second pixel electrode, and comprising a shared continuous amorphous silicon layer that has a thickness less than 40 nm and provides channels for the first thin-film transistor and the second thin-film transistor.

12. The electronic display of claim 11 wherein the display medium is electrophoretic.

13. The electronic display of claim 12 wherein the electrophoretic medium comprises at least one type of particle and a suspending fluid.

14. The electronic display of claim 12 wherein the electrophoretic medium is encapsulated.

15. The electronic display of claim 11 further comprising a light blocking layer provided adjacent to the silicon layer.

16. The electronic display of claim 11 further comprising a first data line in communication with the first transistor and a second data line in communication with the second transistor, wherein a distance between the first transistor and the second transistor is selected to provide an acceptable leakage between the first data line and the second data line.

17. The electronic display of claim 16 wherein a distance between the first pixel electrode and the first data line is selected to provide an acceptable leakage between the first pixel electrode and the first data line.

18. The electronic display of claim 11 wherein the first transistor comprises a gate electrode, a source electrode and a drain electrode and the gate electrode and one of the source electrode and the drain electrode form a capacitor.

20. The method of claim 19 further comprising the step of selecting a spacing between the first transistor and the second transistor to provide an acceptable leakage current between the first transistor and the second transistor.

21. The method of claim 19 further comprising the step of forming a dielectric layer adjacent to the at least one gate electrode.

22. The method of claim 19 wherein the step of providing a substrate comprises unwinding the substrate from a first roll and winding the substrate onto a second roll.

23. The method of claim 21 wherein the steps of forming the dielectric layer, forming the unpatterned silicon layer and forming the source and drain electrodes occur at least partially during one visit of the substrate inside a single deposition chamber.

24. The method of claim 19 further comprising the steps of:

providing a first pixel electrode of an electronic display in communication with the source electrode of the first transistor; and

providing a first data line of the electronic display in communication with the drain electrode of the first transistor.

25. The method of claim 24 further comprising the steps of:

providing a second pixel electrode of an electronic display in communication with the source electrode of the second transistor;

providing a second data line of the electronic display in communication with the drain electrode of the second transistor; and

selecting a geometry of at least one of;

(i) the first data line;

(ii) the second data line;

(iii) the first transistor and (iv) the first pixel electrode, to provide an acceptable leakage current between the first data line and the second data line.

26. The method of claim 24 further comprising the step of selecting a distance between the first pixel electrode and the first data line to provide an acceptable leakage between the first pixel electrode and the first data line.

27. The method of claim 24 further comprising the steps of:

providing a second pixel electrode of an electronic display in communication with the source electrode of the second transistor;

providing a second data line of the electronic display in communication with the drain electrode of the second transistor; and

selecting at least one of;

(i) a distance between the source electrode of the first transistor and the drain electrode of the first transistor;

(ii) a channel width of the first transistor;

(iii) a dimension of the first pixel electrode;

(iv) a distance between the first data line and the first transistor and (v) a distance between the first pixel electrode and the second data line, to provide an acceptable leakage current between the first data line and the second data line.

28. The method of claim 19 wherein the step of forming the unpatterned silicon layer comprises forming an amorphous silicon film.

29. The method of claim 28 wherein the step of forming the unpatterned silicon layer comprises forming an intrinsic amorphous silicon film.

30. The method of claim 19 wherein the steps of forming include mask steps consisting of a first mask step and a second mask step, wherein the step of forming at least one gate electrode comprises the first mask step and the steps of forming at least one patterned drain electrode and forming at least one patterned source electrode share the second mask step.

19. A method of manufacturing an array of thin-film transistors comprising at least a first transistor and a second transistor, the method comprising the steps of:

providing a substrate;

forming adjacent to the substrate an unpatterned silicon layer having a thickness less than 40 nm;

forming at least one patterned drain electrode for each of the transistors, the drain electrodes in direct contact with the unpatterned silicon layer;

forming at least one patterned source electrode for each of the transistors, the source electrodes in direct contact with the unpatterned silicon layer; and

forming at least one gate electrode for each of the transistors, the gate electrode disposed adjacent to the unpatterned silicon layer.