Network switch using network processor and methods

• US 20020061022A1
• Filed: 10/23/2001
• Published: 05/23/2002
• Est. Priority Date: 08/27/1999
• Status: Active Grant

• Current Assignee: Brian Mitchell Bass, Fabrice Jean Verplanken, James Johnson Jr. Allen, Jean Louis Calvignac, Marco C. Heddes, Michael Steven Siegel, Santosh Prasad Gaur
• Original Assignee: Brian Mitchell Bass, Fabrice Jean Verplanken, James Johnson Jr. Allen, Jean Louis Calvignac, Marco C. Heddes, Michael Steven Siegel, Santosh Prasad Gaur
• Inventors: Calvignac, Jean Louis, Siegel, Michael Steven, Verplanken, Fabrice Jean, Heddes, Marco C., Bass, Brian Mitchell, Allen, James Johnson Jr., Gaur, Santosh Prasad
• Granted Patent: US 6,842,443 B2
• Time in Patent Office: Days
• US Class Current: 370/392
• CPC Class Codes: H04L 2212/00 Encapsulation of packets
• CPC Class Codes: H04L 45/742 Route cache; Operation thereof
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/354 for supporting virtual local area networks [VLAN]
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching
• CPC Class Codes: H04Q 2213/1302 Relay switches
• CPC Class Codes: H04Q 2213/13034 A/D conversion, code compression/expansion
• CPC Class Codes: H04Q 2213/1304 Coordinate switches, crossbar, 4/2 with relays, coupling field
• CPC Class Codes: H04Q 2213/13103 Memory
• CPC Class Codes: H04Q 2213/13104 Central control, computer control
• CPC Class Codes: H04Q 2213/13106 Microprocessor, CPU
• CPC Class Codes: H04Q 2213/13107 Control equipment for a part of the connection, distributed control, co-processing
• CPC Class Codes: H04Q 2213/13322 Integrated circuits
• CPC Class Codes: H04Q 3/002 Details
• CPC Class Codes: H04Q 3/5455 Multi-processor, parallelism, distributed systems

Abstract

A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

Claims

1. Apparatus comprising:

a control point processor;

an interface device operatively connected to said control point processor and having;

a semiconductor substrate;

a plurality of interface processors formed on said substrate, the number of said processors being at least five;

internal instruction memory formed on said substrate and storing instructions accessibly to said interface processors;

internal data memory formed on said substrate and storing data passing through said device accessibly to said interface processors; and

a plurality of input/output ports formed on said substrate;

at least one of said input/output ports connecting said internal data memory with external data memory;

at least two other of said input/output ports exchanging data passing through the interface device with an external network under the direction of said interface processors;

said control point processor cooperating with said interface device by loading into said instruction memory instructions to be executed by said interface processors in directing the exchange of data between said data exchange input/output ports and the flow of data through said data memory; and

a self routing switching fabric device operatively connected to said interface device and directing data inbound to the apparatus from identifiable addresses to flow outbound from the apparatus to identified addresses.

2. Apparatus according to claim 1 further comprising:

a second interface device operatively connected to said control point processor and having;

a semiconductor substrate;

a plurality of interface processors formed on said substrate, the number of said processors being at least five;

internal instruction memory formed on said substrate and storing instructions accessibly to said interface processors;

internal data memory formed on said substrate and storing data passing through said device accessibly to said interface processors; and

a plurality of input/output ports formed on said substrate;

at least one of said input/output ports connecting said internal data memory with external data memory;

at least two other of said input/output ports exchanging data passing through the interface device with an external network under the direction of said interface processors;

said control point processor cooperating with said second interface device by loading into said instruction memory instructions to be executed by said interface processors in directing the exchange of data between said data exchange input/output ports and the flow of data through said data memory;

said second interface device being operatively connected to said self routing switching fabric device; and

said interface device and said second interface device being linked one to the other and cooperating so that data flow through the apparatus is divided therebetween.

3. Apparatus according to claim 2 further comprising a second self routing switching fabric device operatively connected to said interface devices and serving as a secondary device to direct data inbound to the apparatus from identifiable addresses to flow outbound from the apparatus to identified addresses in the event of failure of said switching fabric device.

4. Apparatus comprising:

a self routing switching fabric device directing data inbound to the apparatus from identifiable addresses to flow outbound from the apparatus to identified addresses, said switching fabric device having an input port and an output port for data flow therethrough;

a control point processor; and

a plurality of interface devices operatively connected to said switching fabric device and to said control point processor, each of said interface devices having;

a semiconductor substrate;

a plurality of interface processors formed on said substrate, the number of said processors being at least five;

internal instruction memory formed on said substrate and storing instructions accessibly to said interface processors;

internal data memory formed on said substrate and storing data passing through said device accessibly to said interface processors; and

a plurality of input/output ports formed on said substrate;

at least one of said input/output ports connecting said internal data memory with external data memory;

at least two other of said input/output ports exchanging data passing through the interface device with an external network under the direction of said interface processors;

said control point processor cooperating with said interface device by loading into said instruction memory instructions to be executed by said interface processors in directing the exchange of data between said data exchange input/output ports and the flow of data through said data memory; and

a plurality of said interface devices being operatively connected with each of the input and output ports of said switching fabric device.

5. Apparatus according to claim 4 wherein data flowing into said apparatus is passed through an interface device inbound to said switching fabric device.

6. Apparatus according to claim 4 wherein data flowing from said apparatus is passed through an interface device outbound from said switching fabric device.

7. Apparatus according to claim 4 data flowing into said apparatus is passed through an interface device inbound to said switching fabric device and data flowing from said apparatus is passed through an interface device outbound from said switching fabric device.

8. Apparatus comprising:

a self routing switching fabric device directing data inbound to the apparatus from identifiable addresses to flow outbound from the apparatus to identified addresses, said switching fabric device having an input port and an output port for data flow therethrough;

a control point processor; and

an interface device operatively connected to said switching fabric device and to said control point processor, said interface device having;

a semiconductor substrate;

a plurality of interface processors formed on said substrate, the number of said processors being at least five;

internal instruction memory formed on said substrate and storing instructions accessibly to said interface processors;

internal data memory formed on said substrate and storing data passing through said device accessibly to said interface processors; and

a plurality of input/output ports formed on said substrate;

at least one of said input/output ports connecting said internal data memory with external data memory;

at least two other of said input/output ports exchanging data passing through the interface device with an external network under the direction of said interface processors;

at least two other of said input/output ports accomplishing a high speed interconnection between said interface device and said switching fabric device;

said control point processor cooperating with said interface device by loading into said instruction memory instructions to be executed by said interface processors in directing the exchange of data between said data exchange input/output ports and the flow of data through said data memory.

9. Apparatus according to claim 8 wherein each of said high speed interconnection input/output ports has:

a logic circuit which parses a data stream presented as N bits in parallel into a plurality of portions each having n bits, where n is a fraction of N;

a serializer communicating with said logic circuit which serializes each parsed portion of the data stream;

a plurality of channels communicating with said serializer and transferring data streams, the number of said channels being equal to the number of parsed portions and one of said channels being associated with each of said parsed portions of the data stream; and

a deserializer communicating with said channels and which receives serial data streams transferred therethrough and restores the data stream to presentation as N bits in parallel.

10. Apparatus comprising:

a control point processor;

an interface device operatively connected to said control point processor and having;

a semiconductor substrate;

a plurality of interface processors formed on said substrate, the number of said processors being at least five;

internal instruction memory formed on said substrate and storing instructions accessibly to said interface processors;

internal data memory formed on said substrate and storing data passing through said device accessibly to said interface processors; and

a plurality of inpuvoutput ports formed on said substrate;

at least one of said input/output ports connecting said internal data memory with external data memory;

at least two other of said input/output ports exchanging data passing through the interface device with an external network under the direction of said interface processors;

said control point processor cooperating with said interface device by loading into said instruction memory instructions to be executed by said interface processors in directing the exchange of data between said data exchange input/output ports and the flow of data through said data memory; and

said interface device having two high speed interconnection ports, each of which has;

a logic circuit which parses a data stream presented as N bits in parallel into a plurality of portions each having n bits, where n is a fraction of N;

a serializer communicating with said logic circuit which serializes each parsed portion of the data stream;

a plurality of channels communicating with said serializer and transferring data streams, the number of said channels being equal to the number of parsed portions and one of said channels being associated with each of said parsed portions of the data stream; and

a deserializer communicating with said channels and which receives serial data streams transferred therethrough and restores the data stream to presentation as N bits in parallel.

11. Apparatus according to claim 10 wherein each of said high speed interconnection ports is connected to the other of said high speed interconnection ports whereby data flow through said interface device passes from one interface processor thereof through said interconnection ports to another of said interface processors.

12. Apparatus according to claim 10 further comprising a self routing switching fabric device operatively directing data inbound to the apparatus from identifiable addresses to flow outbound from the apparatus to identified addresses and wherein each of said high speed interconnection ports is connected to said switching fabric device whereby data flow through the apparatus passes inbound from one interface processor to said switching fabric device and outbound from said switching fabric device through another interface processor.

14. A method according to claim 10 wherein the step of communicating the data flow through the plurality of interface processors comprises parsing the data flow into portions and distributing the parsed portions among the plurality of interface processors for handling in parallel.

13. A method comprising the steps of:

receiving a data flow inbound through an input port of an interface device;

communicating the inbound data flow through a plurality of interface processors embedded in the interface device;

dividing the inbound data flow into a first portion to be redirected by a switching fabric device and a second portion to be temporarily stored apart from the switching fabric device;

directing the first portion to a switching fabric device and the second portion to a memory element;

receiving the first portion at an interface processor as a data flow outbound from the switching fabric device;

recombining the first and second portions; and

directing the recombined data flow outbound through an output port in accordance with the execution of the instructions by the interface processors.