Semiconductor device and method of manufacturing the same

• US 20020061642A1
• Filed: 01/11/2002
• Published: 05/23/2002
• Est. Priority Date: 09/02/1999
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Sakemi, Shoji, Haji, Hiroshi
• Granted Patent: US 6,683,379 B2
• Time in Patent Office: Days
• US Class Current: 438/613
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

The method of manufacturing a semiconductor device of the present invention includes steps of; a resin layer forming process in which a face with electrodes of a semiconductor wafer having a plurality of semiconductor elements formed thereon is coated with a resin layer which has a function of sealing it; and a wafer thinning process in which the back face of the semiconductor wafer is ground. The method of manufacturing the semiconductor device of the present invention further includes a process of forming a conductive section on the electrodes of the semiconductor wafer with a plurality of semiconductor elements in such a manner the conductive section reaches to the electrodes. The manufacturing method of the semiconductor device of the present invention still further includes a process of cutting the semiconductor wafer having a plurality of semiconductor elements along boundaries of each semiconductor element. In the thinning process, at least one of a mechanical grinding method, a chemical etching method and a plasma etching method are employed.

Claims

1. A method of manufacturing a semiconductor device comprising the steps of;

forming a resin layer having a sealing function on a face with electrodes of a semiconductor wafer which has a plurality of semiconductor elements mounted thereon; and

grinding and thinning a back face of the semiconductor wafer after the resin layer forming process.

2. The method of manufacturing a semiconductor device of claim 1, further comprising a step of forming a conductive section on the electrodes of the semiconductor wafer.

3. The method of manufacturing a semiconductor device of claim 2, in which the conductive section is formed by one of a plating method, a wire bonding method and a method of connecting metallic balls.

4. The method of manufacturing a semiconductor device of claim 1, further comprising a step of cutting the semiconductor wafer along boundaries of the semiconductor elements.

5. The method of manufacturing a semiconductor device of claim 2, further comprising a step of cutting the semiconductor wafer along boundaries of the semiconductor elements.

6. The method of manufacturing a semiconductor device of claim 1, claim 2 or claim 4, in which the thinning process is carried out by at least one of a mechanical grinding method, a chemical etching and a plasma etching.

7. The method of manufacturing a semiconductor device of claim 1, in which the thinning process is carried out by at least one of a mechanical grinding method, a chemical etching and a plasma etching.

8. The method of manufacturing a semiconductor device of claim 2, in which the thinning process is carried out by at least one of a mechanical grinding method, a chemical etching and a plasma etching.

9. The method of manufacturing a semiconductor device of claim 4, in which the thinning process is carried out by at least one of a mechanical grinding method, a chemical etching and a plasma etching.

11. The semiconductor device of claim 6, wherein the resin layer includes at least one of silica, alumina, zirconia, quartz fiber, glass fiber, resin fiber and inorganic particles capable of absorbing ionic impurities.

10. A semiconductor device wherein a resin layer is formed on a face with electrodes of a semiconductor wafer having semiconductor elements, and thickness of the semiconductor wafer is not more than 300 μ

m.