Multi-master computer system with overlapped read and write operations and scalable address pipelining

• US 20020062414A1
• Filed: 05/15/2001
• Published: 05/23/2002
• Est. Priority Date: 06/21/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hofmann, Richard Gerard, Hopp, Jason Michael, Wilkerson, Dennis Charles, LaFauci, Peter Dean
• Granted Patent: US 6,772,254 B2
• Time in Patent Office: Days
• US Class Current: 710/110
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

A multi-master computer system having overlapped read and write signal with scalable address pipelining programmable increases the depth of address pipelining independently on two overlapped read and write data busses up to “N” deep requests. The system includes a local bus having an address bus, a read bus, and a write bus. Master devices are coupled to separate address, read data and write data buses. Slave devices are attached to the data busses through shared, but decoupled address, read and write data buses. An arbiter is coupled to the data bus and allows masters to compete for bus ownership. The arbiter includes read and write pipeline logic for processing and priortizing master and slave read and write data transfers across the data bus. Programming apparatus alters the read and write pipeline logic for address pipelining

Claims

1. A data transfer system with overlapped read and write operations and scalable address pipelining, comprising:

a data bus including an address bus, a read bus, and a write bus;

at least one master device coupled to separate address, read data and write data buses;

at least one slave device attached to the local bus through shared, but decoupled address, read and write data buses;

an arbiter apparatus coupled to the local bus, the arbiter allowing masters to compete for bus ownership; and

scalable logic which programs address pipelining up to “

N”

deep master requests where “

N”

is any positive non-zero integer.

2. The system of claim 1 further comprising:

a read or write master pipeline logic implementing scalable pipeline logic in the arbiter for pipelining data transfers.

3. The system of claim 1 wherein the read or write master pipeline logic comprises:

a series connection of shift register stages for receiving successive master requests for data transfer; and

multiplexers between shift register stages receiving an input from a preceding stage and a master request to select the signal for transfer to the next succeeding stage.

4. The system of claim 1 further comprising:

a read or write slave pipeline logic implementing scalable pipeline logic in the arbiter for pipelining data transfers.

5. The system of claim 4 wherein the read or write slave pipeline logic comprises:

a series connection of shift register stages for receiving successive slave requests for data transfer;

multiplexers between shift register stages receiving an input from a preceding stage and a slave acknowledge to select the signal for transfer to the next succeeding stage; and

a decoder converting a slave identifying signal to an address identifying the slave.

6. The system of claim 1 further comprising:

a read or write priority pipeline logic prioritizing scalable pipeline logic in the arbiter for pipelining data transfers.

7. The system of claim 6 wherein the read or write priority logic comprises:

a secondary register sequentially linked to a third shift register stage and a fourth shift register stage, each stage receiving a Request Priority signal; and

a multiplexer and selectable priority resolution circuit coupled to the secondary register and receiving input signals from the third and fourth stages and the Request Priority signal for loading the secondary register.

8. The system of claim 1 further comprising:

arbiter signal generation appartus which generates signals for implementing scalable address pipelining.

9. The system of claim 8 wherein the signal generation apparatus generates a read pending request signal to indicate that a master or slave has a read request pending on the data bus or a secondary read transfer has been acknowledged and is pending.

10. The system of claim 8 wherein the signal generation apparatus generates a read pending priority signal to indicate the highest priority of any active read request of a master or slave.

11. The system of claim 8 wherein the signal generation apparatus generates a write pending request signal to indicate any active write request on the bus from all masters.

12. The system of claim 9 wherein the signal generation apparatus generates a write pending priority signal to indicate the highest priority of any active write request from all masters or slaves.

14. The system of claim 1 further comprising:

arbiter notifying apparatus which notifies the proper slave that its pipeline transfer is considered primary and that the slave may latch or drive the data bus depending on whether a drived or latch operation is pipelined.

15. The system of claim 1 further comprising:

arbiter information apparatus which provides information to all bus masters as to the highest priority pending read request and write request in an acknowledged pipeline queue.

17. The method of claim 16 further comprising the step of:

generating a read pending request signal to indicate that a master has a read request pending on the data bus or a secondary read transfer has been acknowledged and is pending.

18. The method of claim 16 further comprising the step of:

generates a read pending priority signal to indicate the highest priority of any active read request of a master.

19. The method of claim 16 further comprising the step of:

generating a write pending request signal to indicate the highest priority of any active write request on the data bus from all masters or slaves.

20. The method of claim 16 further comprising the step of:

generating a write pending priority signal to indicate the highest priority of any active write request from all masters or a secondary write request has been acknowledged and is pending.

21. The method of claim 16 further comprising the step

tracking the master and slave involved in each pipeline transfer to ensure that the transfers were broadcast and acknowledged.

22. The method of claim 16 further comprising the step of

notifying the proper slave that its pipeline transfer is considered primary and that the slave may latch or drive the data bus depending on whether a drive or latch operation is pipelined.

23. The method of claim 16 further comprising the step

providing information to all bus masters as to the highest priority pending read request and write request in an acknowledged pipeline queue.

24. The method of claim 16 further comprising the step of Generating

signals for implementing scalable address pipelining.

26. The medium of claim 25 further comprising:

program instructions generating a read pending request signal to indicate that a master or slave has a read request pending on the data bus or a secondary read transfer has been acknowledged and is pending.

27. The medium of claim 25 further comprising:

program instructions programmably changing the depth of address pipelining independently on the overlapped read and write data busses.

28. The medium of claim 25 further comprising:

program instructions generating a read pending priority signal to indicate the highest priority of any active read request of a master or slave.

29. The medium of claim 25 further comprising:

program instructions generating a write pending request signal to indicate the highest priority of any active write request on the data bus from all masters.

30. The medium of claim 25 further comprising:

program instructions generating a write pending priority signal to indicate the highest priority of any active write request from all masters.

31. The medium of claim 25 further comprising:

program instructions tracking the master and slave involved in each pipeline transfer to ensure that the transfers were broadcast and acknowledged.

32. The medium of claim 25 further comprising:

program instructions notifying the proper slave that its pipeline transfer is considered primary and that the slave may latch or drive the data bus depending on whether a drive or latch operation is pipelined.

33. The medium of claim 25 further comprising:

program instructions providing information to all bus masters as to the highest priority pending read request and write request in an acknowledged pipeline queue.

34. The medium of claim 25 further comprising:

program instructions generating signals for implementing scalable address pipelining.

13. The system of Claim l further comprising:

Arbiter tracking apparatus which tracks the master and slave involved in each pipeline transfer to broadcast and acknowledge.

16. A method of data transfer in a multi-computer system with overlapped read and write operations and scalable address pipelining, comprising the steps of:

generating signals for address, read and write transfers across a data bus;

loading and shifting of master request in a master pipeline logic;

loading and shifting an acknowledgement of a data request in a slave pipeline logic;

advancing the next slave in the pipeline upon completion of a primary data transfer;

recording the transfer of data in an arbiter pipeline logic;

Loading the highest priority value in the priority pipeline logic for execution by a master device or slave device as the case may be; and

programmably changing the the depth of address pipelining independently on the overlapped read and write data busses.

25. A program medium, executable in a computer system for data transfers in a multi-computer system with overlapped read and write operations and scalable address pipelining, comprising:

program instructions generating signals for address, read and write transfers across a data bus;

program instructions loading and shifting of master request in a master pipeline logic;

program instructions loading and shifting an acknowledgement of a data request in a slave pipeline logic;

program instructions advancing the next slave in the pipeline upon completion of a primary data transfer;

program instructions recording the transfer of data in an arbiter pipeline logic;

program instructions loading the highest priority value in the priority pipeline logic for execution by a master device ; and

program instructions programmably changing the depth of address pipelining independently on the overlapped read and write data busses.