Enhanced grading and sorting of semiconductor devices using modular "plug-in" sort algorithms

• US 20020063085A1
• Filed: 01/22/2002
• Published: 05/30/2002
• Est. Priority Date: 03/30/1999
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Capser, Lance M.
• Granted Patent: US 6,747,228 B2
• Time in Patent Office: Days
• US Class Current: 209/573
• CPC Class Codes: G11C 29/54 Arrangements for designing test circuits, e.g. design for test [DFT] tools
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A semiconductor device sorting method and apparatus involve development of small, self-contained and focused “qualification” or “sort” algorithm test programs or “modules”, each of which modules may test for the validity of a particular, selected grade of a memory or other semiconductor device based on the results of a test pattern associated with, or exhibited by, a particular device under test. Separating the test code from the main flow file of the test program into the aforementioned “plug-in” qualification or sort modules permits the test code to be much simpler and facilitates better organization, as each qualification or sort module may be independent of any other qualification or sort module and only determines in response to its associated test pattern whether or not (TRUE or FALSE) a device qualifies in a given device grade.

Claims

1. A method of qualifying and sorting semiconductor devices, comprising:

grouping a plurality of semiconductor devices into a test lot;

selecting a plurality of device grades and a downgrade path for each selected device grade;

selecting a test sequence including a plurality of tests, each test corresponding to at least one device grade of the plurality of device grades;

defining an initial selected device grade of the plurality of device grades for the test lot;

sorting each semiconductor device in the test lot to a final device grade of the plurality of device grades, said sorting comprising;

executing substantially each test in the test sequence on each semiconductor device; and

after each test executed, sequentially sorting each semiconductor device through the plurality of selected device grades along a selected downgrade path; and

separating the plurality of semiconductor devices from the test lot according to the final device grade of each semiconductor device.

2. The method of claim 1, further comprising sequentially sorting only those semiconductor devices through the plurality of selected device grades that fail a test which is not constrained to the device grade corresponding to the failed test.

3. A method of qualifying and sorting semiconductor devices, comprising:

selecting a plurality of device grades and a downgrade path for each selected device grade;

selecting a first test to be performed on at least one semiconductor device;

executing the first test on the at least one semiconductor device to cause the at least one semiconductor device to exhibit a test pattern responsive thereto; and

sequentially sorting the at least one semiconductor device through at least two of the plurality of selected device grades along at least one downgrade path responsive to the exhibited test pattern by sequentially comparing the exhibited test pattern to a discrete set of criteria relating to the first test for each of the at least two selected device grades.

4. A method of qualifying and sorting semiconductor devices, comprising:

selecting a plurality of device grades and a downgrade path for each selected device grade; and

sequentially sorting at least one semiconductor device through the plurality of selected device grades along a selected downgrade path solely according to the result of a first test pattern exhibited by the at least one semiconductor device responsive to a first test associated with a first test register selected by a test program.

5. The method of claim 4, further comprising:

sequentially sorting the semiconductor device through a plurality of selected device grades along a selected downgrade path solely according to the result of a second test pattern exhibited by the semiconductor device responsive to a second, different test associated with a second test register selected by the test program.