Ferroelectric memory device and method of fabricating the same
First Claim
1. A ferroelectric memory device comprising:
- first and second switching elements formed on a semiconductor substrate;
an interlayer insulating layer formed on a resulting structure where the first and second switching elements are formed; and
first and second ferroelectric capacitors having at least three electrode layers, the first and second ferroelectric capacitors being sequentially stacked on the interlayer insulating layer, wherein the first ferroelectric capacitor includes a lower electrode formed on the interlayer insulating layer, a first ferroelectric layer formed on the lower electrode, and a middle electrode formed on the first ferroelectric layer; and
wherein the second ferroelectric capacitor includes the middle electrode, a second ferroelectric layer formed on the middle electrode, and an upper electrode formed on the second ferroelectric layer.
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Abstract
A ferroelectric memory device having a multi-layer electrode structure and a fabricating method thereof are described. The ferroelectric memory device includes a semiconductor substrate having first and second transistors, an interlayer insulating layer covering the first and second transistors, and first and second ferroelectric capacitor sequentially stacked on the interlayer insulating layer. The first ferroelectric capacitor includes a lower electrode, a first ferroelectric layer, and a middle electrode sequentially stacked on the interlayer insulating layer, while the second ferroelectric capacitor includes the middle electrode, and a second ferroelectric layer and an upper electrode sequentially stacked on the middle electrode. First and second transistors are selectively connected to the first and second ferroelectric capacitors, respectively, forming two or one unit cell. Therefore, it is possible to form a unit cell in a smaller area than a conventional area, and increase an area that a capacitor occupies.
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Citations
23 Claims
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1. A ferroelectric memory device comprising:
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first and second switching elements formed on a semiconductor substrate;
an interlayer insulating layer formed on a resulting structure where the first and second switching elements are formed; and
first and second ferroelectric capacitors having at least three electrode layers, the first and second ferroelectric capacitors being sequentially stacked on the interlayer insulating layer, wherein the first ferroelectric capacitor includes a lower electrode formed on the interlayer insulating layer, a first ferroelectric layer formed on the lower electrode, and a middle electrode formed on the first ferroelectric layer; and
wherein the second ferroelectric capacitor includes the middle electrode, a second ferroelectric layer formed on the middle electrode, and an upper electrode formed on the second ferroelectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of fabricating a ferroelectric memory device comprising the steps of:
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forming first and second switching elements on a semiconductor substrate;
forming an interlayer insulating layer covering the first and second switching elements;
forming first and second contact plugs in the interlayer insulating layer, the first and second contact plugs being coupled to the first and second switching elements, respectively;
forming, on the interlayer insulating layer, capacitors where a lower electrode coupled to the first contact plug, a first ferroelectric layer, a middle electrode, a second ferroelectric layer, and an upper electrode are sequentially stacked;
forming an insulating layer covering the capacitor, the second contact plug, and the interlayer insulating layer; and
forming, in the insulating layer, an interconnection for connecting the second contact plug to the upper electrode. - View Dependent Claims (10, 11, 12, 13, 15, 16, 17, 18, 20, 21, 22, 23)
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14. A method of fabricating a ferroelectric memory device comprising the steps of:
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forming a switching element on a semiconductor substrate;
forming an interlayer insulating layer covering the switching element;
forming a contact plug coupled to the switching element in the interlayer insulating layer;
forming, on the interlayer insulating layer, first and second capacitors comprising a lower electrode, a first ferroelectric layer, a middle electrode, a second ferroelectric layer, and an upper electrode;
forming an insulating layer covering the first and second capacitors, the contact plug, and the interlayer insulating layer; and
forming an interconnection for connecting the contact plug to the middle electrode in the insulating layer.
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19. A method of fabricating a ferroelectric memory device comprising the steps of:
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forming a switching element on a semiconductor substrate;
forming an interlayer insulating layer covering the switching element;
forming a contact plug coupled to the switching element in the interlayer insulating layer;
forming, on the interlayer insulating layer, first and second capacitors comprising a lower electrode coupled to the contact plug, a first ferroelectric layer, a middle electrode, a second ferroelectric layer, and an upper electrode sequentially stacked;
forming an insulating layer covering the first and second capacitors and the interlayer insulating layer; and
forming an interconnection for connecting the lower electrode to the upper electrode in the insulating layer.
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Specification