Ferroelectric memory device and method of fabricating the same

• US 20020063271A1
• Filed: 10/30/2001
• Published: 05/30/2002
• Est. Priority Date: 11/21/2000
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Hyun-Ho
• Granted Patent: US 6,617,628 B2
• Time in Patent Office: Days
• US Class Current: 257/295
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A ferroelectric memory device having a multi-layer electrode structure and a fabricating method thereof are described. The ferroelectric memory device includes a semiconductor substrate having first and second transistors, an interlayer insulating layer covering the first and second transistors, and first and second ferroelectric capacitor sequentially stacked on the interlayer insulating layer. The first ferroelectric capacitor includes a lower electrode, a first ferroelectric layer, and a middle electrode sequentially stacked on the interlayer insulating layer, while the second ferroelectric capacitor includes the middle electrode, and a second ferroelectric layer and an upper electrode sequentially stacked on the middle electrode. First and second transistors are selectively connected to the first and second ferroelectric capacitors, respectively, forming two or one unit cell. Therefore, it is possible to form a unit cell in a smaller area than a conventional area, and increase an area that a capacitor occupies.

Claims

1. A ferroelectric memory device comprising:

first and second switching elements formed on a semiconductor substrate;

an interlayer insulating layer formed on a resulting structure where the first and second switching elements are formed; and

first and second ferroelectric capacitors having at least three electrode layers, the first and second ferroelectric capacitors being sequentially stacked on the interlayer insulating layer,

wherein the first ferroelectric capacitor includes a lower electrode formed on the interlayer insulating layer, a first ferroelectric layer formed on the lower electrode, and a middle electrode formed on the first ferroelectric layer; and

wherein the second ferroelectric capacitor includes the middle electrode, a second ferroelectric layer formed on the middle electrode, and an upper electrode formed on the second ferroelectric layer.

2. The device of claim 1, wherein the first and second switching elements are first and second MOS transistors, respectively.

3. The device of claim 2, wherein the lower electrode is electrically connected to a source region of the first MOS transistor, and the upper electrode is electrically connected to a source region of the second MOS transistor.

4. The device of claim 3 further comprising a plate line that is electrically connected to the middle electrode.

5. The device of claim 2, wherein the middle electrode is electrically connected to one of the source regions of the first and second MOS transistors.

6. The device of claim 5 further comprising first and second plate lines that are electrically connected to the lower and upper electrodes, respectively.

7. The device of claim 2, wherein the lower and upper electrodes are electrically connected to the respective source regions of the first and second MOS transistors.

8. The device of claim 7 further comprising a plate line that is electrically connected to the middle electrode.

9. A method of fabricating a ferroelectric memory device comprising the steps of:

forming first and second switching elements on a semiconductor substrate;

forming an interlayer insulating layer covering the first and second switching elements;

forming first and second contact plugs in the interlayer insulating layer, the first and second contact plugs being coupled to the first and second switching elements, respectively;

forming, on the interlayer insulating layer, capacitors where a lower electrode coupled to the first contact plug, a first ferroelectric layer, a middle electrode, a second ferroelectric layer, and an upper electrode are sequentially stacked;

forming an insulating layer covering the capacitor, the second contact plug, and the interlayer insulating layer; and

forming, in the insulating layer, an interconnection for connecting the second contact plug to the upper electrode.

10. The method of claim 9 further comprising a step of forming a plate line coupled to the middle electrode in the insulating layer.

11. The method of claim 9, wherein the lower, middle, and the upper electrodes are made of one selected from a group consisting of platinum, iridium oxide, ruthenium oxide, and LaSrCo oxide (LSCO), respectively.

12. The method of claim 11, wherein the lower electrode is formed of a multi-layer comprising a titanium layer, a titanium nitride layer, an iridium layer, an iridium oxide layer, and a platinum layer sequentially stacked.

13. The method of claim 9, wherein the ferroelectric layer is made of one selected from a group consisting of lead zirconia titanate (PZT), lead lanthanum zirconia titanate (PLZT), strontium barium titanate (SBT), and barium lanthanum titanate (BLT).

15. The method of claim 14 further comprising a step of forming, in the insulating layer, a first plate line coupled to the lower electrode and a second plate line coupled to the upper electrode.

16. The method of claim 14, wherein the lower, middle, and the upper electrodes are made of one selected from a group consisting of platinum, iridium oxide, ruthenium oxide, and LaSrCo oxide (LSCO), respectively.

17. The method of claim 16, wherein the lower electrode is formed of a multi-layer comprising a titanium layer, a titanium nitride layer, an iridium layer, an iridium oxide layer, and a platinum layer sequentially stacked.

18. The method of claim 14, wherein the ferroelectric layer is made of one selected from a group consisting of lead zirconia titanate (PZT), lead lanthanum zirconia titanate (PLZT), strontium barium titanate (SBT), and barium lanthanum titanate (BLT).

20. The method of claim 19 further comprising a step of forming a plate line coupled to the middle layer in the insulating layer.

21. The method of claim 19, wherein the lower, middle, and the upper electrodes are made of one selected from a group consisting of platinum, iridium oxide, ruthenium oxide, and LaSrCo oxide (LSCO), respectively.

22. The method of claim 21, wherein the lower electrode is formed of a multi-layer comprising a titanium layer, a titanium nitride layer, an iridium layer, an iridium oxide layer, and a platinum layer sequentially stacked.

23. The method of claim 19, wherein the ferroelectric layer is made of one selected from a group consisting of lead zirconia titanate (PZT), lead lanthanum zirconia titanate (PLZT), strontium barium titanate (SBT), and barium lanthanum titanate (BLT).

14. A method of fabricating a ferroelectric memory device comprising the steps of:

forming a switching element on a semiconductor substrate;

forming an interlayer insulating layer covering the switching element;

forming a contact plug coupled to the switching element in the interlayer insulating layer;

forming, on the interlayer insulating layer, first and second capacitors comprising a lower electrode, a first ferroelectric layer, a middle electrode, a second ferroelectric layer, and an upper electrode;

forming an insulating layer covering the first and second capacitors, the contact plug, and the interlayer insulating layer; and

forming an interconnection for connecting the contact plug to the middle electrode in the insulating layer.

19. A method of fabricating a ferroelectric memory device comprising the steps of:

forming a switching element on a semiconductor substrate;

forming an interlayer insulating layer covering the switching element;

forming a contact plug coupled to the switching element in the interlayer insulating layer;

forming, on the interlayer insulating layer, first and second capacitors comprising a lower electrode coupled to the contact plug, a first ferroelectric layer, a middle electrode, a second ferroelectric layer, and an upper electrode sequentially stacked;

forming an insulating layer covering the first and second capacitors and the interlayer insulating layer; and

forming an interconnection for connecting the lower electrode to the upper electrode in the insulating layer.