Semiconductor device and manufacturing method of the same

• US 20020063300A1
• Filed: 11/28/2001
• Published: 05/30/2002
• Est. Priority Date: 11/29/2000
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Miyajima, Takeshi
• Granted Patent: US 6,476,458 B2
• Time in Patent Office: Days
• US Class Current: 257/409
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device has an element region including MOS structure. A p-well region, a connecting impurity diffused region, and an impurity diffused region for guard ring are formed in an n-type semiconductor layer so as to form a well region. The well region has a step defining a higher portion and a lower portion lower than the higher portion so that the impurity diffused region for guard ring is located at the lower portion. The lower portion is located at a periphery of the element region. In this structure, the impurity diffused region for guard ring is completely depleted while the connecting impurity diffused region is partially depleted so that a portion having carriers remains therein while a depletion layer expands in the connecting impurity diffused region before a breakdown due to a reverse bias occurs in the element region.

Claims

1. A semiconductor device comprising:

an element region formed on a substrate;

an impurity diffused guard ring formed at a periphery of the element region in the substrate, and being designed so as to be completely depleted before a breakdown occurs at the element region;

a connecting impurity diffused region formed between the impurity diffused guard ring and the element region so as to connect the impurity diffused guard ring to the element region, the connecting impurity diffused region having a higher impurity concentration in comparison with the impurity diffused guard ring, and the connecting impurity diffused region being not completely depleted at a surface portion thereof when the breakdown occurs at the cell region; and

a step formed approximately at a boundary portion that is formed between the impurity diffused guard ring and the connecting impurity diffused region, the step having a lower portion and a higher portion higher than the lower portion so that the impurity diffused guard ring is located at the lower portion and the connecting impurity diffused region is located at the higher portion, wherein;

an upper limit side of a depletion layer expanding in the connecting impurity diffused region is higher than a principal surface of the impurity guard ring, the upper limit side is disposed at such a level that the depletion layer is capable of reaching in the connecting impurity diffused region, and the connecting impurity diffused region is terminated at a wall of the step that is interposed between the lower portion and higher portion of the step.

2. A semiconductor device according to claim 1, further comprising a field plate extended from the element region to the step.

3. A semiconductor device comprising:

an element region formed on a substrate having a semiconductor layer with a first conductivity;

a guard ring region with a second conductivity formed in the semiconductor layer, located at a periphery of the element region;

a connecting region with the second conductivity formed in the semiconductor layer so as to contact with the guard ring region, the connecting region having higher impurity concentration in comparison with the guard ring region, and the connecting region being not completely depleted at a surface portion thereof when the breakdown occurs at the cell region;

an electrode contacting with the connecting region, for applying a reverse bias to a pn junction formed between a portion with the first conductivity and a portion with the second conductivity in the substrate, wherein when the reverse bias is applied to the pn junction, the guard ring region is completely depleted while the connecting region is partially depleted so as to form a depletion portion and a carrier remaining portion disposed on the depletion region; and

a step formed at a surface portion of the substrate so as to terminate an upper limit side of the depletion portion at a contour thereof which is disposed lower than a standard plane of the substrate.

4. A semiconductor device comprising:

a substrate having a semiconductor layer with a first conductivity, defining an element region and a peripheral region surrounding the element region therein;

a well region with a second conductivity formed in the semiconductor layer, extending from the element region to the peripheral region, having a step at a side of the peripheral region so that a surface of the well region is partially lowered in comparison with a standard plane of the substrate.

5. A semiconductor device according to claim 4, further comprising an electrode contacting with a higher portion in the well region that is defined by the step.

6. A semiconductor device according to claim 5, wherein a depletion layer expands in the well region so that boundary between the depletion layer and a non-depleted layer is terminated at a wall portion of the step.

7. A semiconductor device according to claim 5, wherein the electrode extends to a lower portion in the well region that is defined by the step.

8. A semiconductor device according to claim 6, wherein the electrode extends to a lower portion in the well region that is defined by the step.

9. A semiconductor device according to claim 7, the electrode does not extend to an outer of the well region.

10. A semiconductor device according to claim 8, the electrode does not extend to an outer of the well region.

11. A semiconductor device according to claim 5, wherein an upper limit side of a depletion layer expanding in the well region is higher than a lowered surface of the well region.

12. A semiconductor device according to claim 11, wherein a height of the step is larger than a depth of a remaining region in the well region that is defined by the depletion layer.

14. A semiconductor device according to claim 13, wherein:

when such a reverse bias that a breakdown occurs in the cell region is applied between the well regions and the substrate, the guard ring region is completely depleted while the connecting region is partially depleted so that an upper limit of a depletion layer expanding in the connecting region becomes higher than a principal surface of the guard ring region.

15. A semiconductor device according to claim 13, wherein the connecting region is terminated at one of the wall portion and the lower portion of the step.

16. A semiconductor device according to claim 13, wherein the lower portion of the step extends to an end of the substrate.

17. A semiconductor device according to claim 13, wherein the guard ring region, the connecting region and the at least one of the well regions form a wide well region having the second conductive type and a predetermined width, the wide well region has a low land where the guard ring portion is located and a high land where the connecting portion and the at least one of the well regions are located, wherein the lowland and highland are caused by the step, and a width of the lowland is narrower than that of the highland.

19. A manufacturing method according to claim 18, wherein the step arrangement is formed using at least one of an etching and oxidizing.

20. A manufacturing method according to claim 18, wherein the etching is performed by at least one of a dry process or a wet process.

21. A manufacturing method according to claim 18, wherein a LOCOS process is employed in the oxidizing.

13. A semiconductor device comprising:

a substrate;

a cell region formed on the substrate, acting as a device and having well regions therein that have a second conductive type;

a guard ring region formed at a periphery of the cell region in the substrate, having the second conductive type so as to define a pn junction with the substrate;

a connecting region located between the guard ring region and at least one of the well regions so as to connect the guard ring region to the at least one of the well regions, the connecting region having the second conductive type;

a step formed approximately at a boundary portion that is formed between the guard ring region and the connecting region so that the impurity diffused guard ring is disposed at a lower portion thereof and the connecting impurity diffused region is disposed at a higher portion that is higher than the lower portion with a wall portion interposed therebetween so that the guard ring region is located at the lower portion.

18. A manufacturing method of a semiconductor device, comprising the steps of:

providing a substrate;

forming an impurity diffused guard ring at a periphery of an element region in the substrate;

forming a connecting impurity diffused region between the impurity diffused guard ring and the element region so as to connect the impurity diffused guard ring to the element region, and so as to have a higher impurity concentration in comparison with the impurity diffused guard ring; and

forming a step arrangement approximately at a boundary portion that is defined between the impurity diffused guard ring and the connecting impurity diffused region so as to define a lower portion and a higher portion higher than the lower portion so that the impurity diffused guard ring is located at the lower portion and the connecting impurity diffused region is located at the higher portion thereof.