Controlling the system time clock of an MPEG decoder
First Claim
1. A device for controlling a system time clock (STC) signal of an MPEG decoder comprising:
- a first subtractor receiving a plurality of program clock reference (PCR) values and a plurality of STC values, and outputting first gap values being a difference between a respectively received PCR and STC values;
a controller determining whether a current PCR value has been updated two or more times;
a plurality of difference (DIF) registers storing successively output first gap values of the first subtractor if the current PCR value has not been updated two or more times under the control of the controller;
a second subtractor calculating a second gap value being a difference between a current output value of the first subtractor and the first gap value previously stored in the plurality of DIF registers if the PCR value has been updated two or more times, and storing successively calculated second gap values in a plurality of gap registers;
a mean calculator calculating a mean value of the second gap values stored in the gap registers and outputting an output value;
an LPF/gain controller processing the output value from the mean calculator by performing low pass filtering and gain control;
a voltage controlled oscillator outputting a clock signal having a desired frequency by receiving a value from the LPF/gain controller; and
a temporary STC counter counting based on the clock signal, to output the STC value to the first subtractor.
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Accused Products
Abstract
During decoding and processing of program clock reference (PCR) values in MPEG-2 transport streams, a first initial difference value is obtained by calculating a difference between a first detected PCR value and a system time clock (STC) value generated when the first PCR value is detected. Depending on the update status of the PCR values, a second initial difference value is obtained by calculating a difference between a second detected PCR value and a STC value generated when the second PCR value is detected. Thereafter, a composite difference value is obtained by further calculating a difference between the first initial difference value and the second initial difference value. Subsequently, the first and second initial difference values, and the composite difference values are calculated for a predetermined number of detected PCR values so that the decoder clock signal is generated and maintained at approximately the same frequency as an encoder clock signal.
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Citations
19 Claims
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1. A device for controlling a system time clock (STC) signal of an MPEG decoder comprising:
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a first subtractor receiving a plurality of program clock reference (PCR) values and a plurality of STC values, and outputting first gap values being a difference between a respectively received PCR and STC values;
a controller determining whether a current PCR value has been updated two or more times;
a plurality of difference (DIF) registers storing successively output first gap values of the first subtractor if the current PCR value has not been updated two or more times under the control of the controller;
a second subtractor calculating a second gap value being a difference between a current output value of the first subtractor and the first gap value previously stored in the plurality of DIF registers if the PCR value has been updated two or more times, and storing successively calculated second gap values in a plurality of gap registers;
a mean calculator calculating a mean value of the second gap values stored in the gap registers and outputting an output value;
an LPF/gain controller processing the output value from the mean calculator by performing low pass filtering and gain control;
a voltage controlled oscillator outputting a clock signal having a desired frequency by receiving a value from the LPF/gain controller; and
a temporary STC counter counting based on the clock signal, to output the STC value to the first subtractor. - View Dependent Claims (2, 3, 4)
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5. A method for controlling a system time clock (STC) of an MPEG decoder comprising the steps of:
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increasing a temporary STC value to a desired frequency through an initial reset step;
detecting the presence of a program clock reference (PCR) value in a digital data stream to load the detected PCR value as the temporary STC value;
first calculating a difference between each subsequently detected PCR value and the loaded temporary STC value to obtain first resultant values;
first determining whether a currently detected PCR value has been updated two or more times;
storing the first resultant values when the first determination result indicates the currently detected PCR values have not been updated two or more times and returning to the detecting step;
second calculating gap values between a current first resultant value and the stored first resultant values to obtain second resultant values;
updating the first resultant values and storing the second resultant values;
second determining whether a predetermined number of the detected PCR values have been updated two or more times;
obtaining a mean value of the stored second resultant values if the second determination result indicates the predetermined number of the detected PCR values have been updated two or more times;
returning to the detecting step of the PCR values if the second determination result indicated the predetermined number of the detected PCR values have not been updated two or more times; and
outputting a controlled clock signal with a desired frequency based on the mean value of the second resultant values.
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6. A device for controlling a system time clock (STC), comprising:
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a plurality of program clock registers to temporarily store a plurality of program clock reference (PCR) values;
a temporary STC counter to count an STC value based on a control clock signal;
temporary STC registers to temporarily store the plurality of temporary STC values counted by the temporary STC counter;
a micro-controller unit (MCU) to calculate a gap value being a difference between a respectively received PCR values and STC values stored in the temporary STC registers;
a plurality of difference registers (DIF) to temporarily store a plurality of first resultant values generated from the gap value between the PCR and STC values of the MCU;
a plurality of gap registers to temporarily store second resultant values generated by calculating a gap value between a current and previous first resultant value stored in the DIF registers;
a controller to check whether all the PCR values have been updated two or more times;
a pulse width modulator (PWM) controller generating a mean value of a predetermined number of the second based resultant values;
an LPF/gain controller to perform low pass filtering and gain control of output from the PWM controller; and
a voltage controlled oscillator to output the control clock signal based on output of the the LPF/gain controller. - View Dependent Claims (7)
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8. A method for controlling a system time clock (STC) of an MPEG decoder comprising the steps of:
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detecting respective program clock register (PCR) values and respectively storing the detected PCR values and a temporary STC value;
implementing an interrupt operation to read out the PCR value and the temporary STC counter value and respectively calculating first resultant values of (PCR value—
STC value) and second resultant values of (a current first resultant value—
a previous first resultant value);
storing the calculated first resultant values in a corresponding register and storing the second resultant values in a corresponding register;
determining whether a predetermined number of the PCR values have been updated two or more times;
obtaining a mean value of the second resultant values and storing the mean value when the determining step determines that the predetermined number of the PCR values have been updated two or more times;
outputting a controlled clock of a desired frequency using the stored mean value; and
generating the temporary STC value based on the controlled clock. - View Dependent Claims (9, 10)
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11. An apparatus for generating a decoder clock signal, comprising:
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a detector detecting a plurality of program clock reference (PCR) values encoded by an encoder clocked using an encoder clock signal;
a processor generating a first initial difference value by calculating a difference between a first detected PCR value and a system time clock (STC) value generated when the first PCR value was detected;
the processor generating a second initial difference value by calculating a difference between a second detected PCR value and a STC value generated when the second PCR value was detected;
the processor generating a composite difference value by calculating a difference between the first initial difference value and the second initial difference value;
an oscillator generating a decoder clock signal based on the composite difference value;
a counter generating the system time clock values based on the decoder clock signal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification