High performance system-on-chip using post passivation process
First Claim
Patent Images
1. A method for forming an inductor for high performance integrated circuits overlaying the surface of a semiconductor substrate, comprising:
- providing a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;
creating an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;
depositing a passivation layer over said overlaying interconnecting metalization structure;
depositing a polymer insulating, separating layer over said passivation layer that is substantially thicker than said passivation layer and that is also substantially thicker than an inter-layer dielectric used for creating said interconnecting metallization structure;
forming openings through said polymer insulating, separating layer and through said passivation layer to expose at least one pair of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure;
filling said openings with a conductive material, creating metal contacts through said openings; and
forming said inductor on the surface of said polymer insulating, separating layer, said inductor being connected to at least one pair of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure.
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Abstract
The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.
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Citations
86 Claims
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1. A method for forming an inductor for high performance integrated circuits overlaying the surface of a semiconductor substrate, comprising:
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providing a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;
creating an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;
depositing a passivation layer over said overlaying interconnecting metalization structure;
depositing a polymer insulating, separating layer over said passivation layer that is substantially thicker than said passivation layer and that is also substantially thicker than an inter-layer dielectric used for creating said interconnecting metallization structure;
forming openings through said polymer insulating, separating layer and through said passivation layer to expose at least one pair of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure;
filling said openings with a conductive material, creating metal contacts through said openings; and
forming said inductor on the surface of said polymer insulating, separating layer, said inductor being connected to at least one pair of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 66, 67, 68, 79, 80, 83, 84)
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10. A method for forming a capacitor for high performance integrated circuits on the surface of a semiconductor substrate, said capacitor comprising a top plate and a bottom plate and a layer of dielectric interspersed between said top and said bottom plate, comprising:
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providing a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;
creating an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate, said points of electrical contact provided on the surface of said overlaying interconnecting metalization structure being divided into pairs of even and odd numbered adjacent contact points whereby one point of electrical contact can belong to only one pair;
depositing a passivation layer over said overlaying interconnecting metalization structure;
patterning and etching said layer of passivation, creating openings in said layer of passivation, at least one opening overlaying at least one even contact point of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure;
depositing a first layer of conductive material over the surface of said layer of passivation, including said openings created in said layer of passivation;
patterning and etching said first layer of conductive material creating an opening to at least one of said even numbered points of electrical contact provided in or on the surface of said overlaying interconnecting metalization structure, creating said bottom plate of said capacitor;
depositing a layer of dielectric over the surface of said first layer of conductive material, including said opening to at least one of said even numbered points of electrical contact;
patterning and etching said layer of dielectric, creating an opening in said layer of dielectric to at least one of said even numbered points of electrical contact, partially exposing at least one of said even numbered points of electrical contact, creating said layer of dielectric interspersed between said top plate and said bottom plate;
depositing a second layer of conductive material over the surface of said layer of dielectric, including at least one opening created in said layer of dielectric; and
patterning and etching said second layer of conductive material, creating said top plate of said capacitor. - View Dependent Claims (11, 12, 13, 16, 17, 18, 19, 20, 69, 70)
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14. A method for forming a resistor for high performance integrated circuits on the surface of a semiconductor substrate, comprising:
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providing a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;
creating an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;
depositing a passivation layer over said overlaying interconnecting metalization structure;
patterning and etching said layer of passivation, creating openings in said layer of passivation, at least two of said openings overlaying at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization;
depositing a layer of conductive material over the surface of said layer of passivation, including said openings created in said layer of passivation;
patterning and etching said layer of resistive conducting material, creating a layer of conductive material that interconnects at least one pair of said openings created in said layer of passivation, creating said resistor.
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15. A method for forming a resistor for high performance integrated circuits on the surface of a semiconductor substrate, comprising:
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providing a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;
creating an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;
depositing a passivation layer over said overlaying interconnecting metalization structure;
patterning and etching said layer of passivation, creating openings in said layer of passivation, at least two of said openings overlaying and partially exposing at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure;
depositing an polymer insulating, separating layer over the surface of said patterned and etched layer of passivation, including said openings created in said layer of passivation;
patterning and etching said polymer insulating, separating layer, creating at least one pair of openings in said polymer insulating, separating layer that aligns with at least one pair of openings created in said layer of passivation, partially exposing at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure;
depositing a layer of conductive material over the surface of said polymer insulating, separating layer including said openings created in said polymer insulating, separating layer; and
patterning and etching said layer of resistive conducting material, creating a layer of conductive material that interconnects at least one pair of said openings created in said layer of passivation, creating said resistor.
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21. A method for mounting a discrete electrical component above the surface of a semiconductor substrate, comprising:
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providing a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;
creating an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;
depositing a passivation layer over said overlaying interconnecting metalization structure;
patterning and etching said layer of passivation, creating openings in said layer of passivation, at least two of said openings overlaying at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure, providing at least one pair of points of electrical contact in said layer of passivation;
depositing an polymer insulating, separating layer over the surface of said patterned and etched layer of passivation, including said openings created in said layer of passivation;
patterning and etching said polymer insulating, separating layer, creating at least one pair of openings in said polymer insulating, separating layer that aligns with at least one pair of points of electrical contact provided in said layer of passivation;
selectively depositing a layer of conductive material over the surface of at least one pair of points of electrical contact provided in said layer of passivation, filling said openings created in said polymer insulating, separating layer, creating conductive plugs through said polymer insulating, separating layer, said conductive plugs overlaying at least one pair of points of electrical contact provided in said layer of passivation;
selectively creating a layer of solder over the surface of said conductive plugs;
positioning said discrete electrical component above and in alignment with said selectively created layer of solder such that electrical contact points of said discrete electrical component align with said selectively created layer of solder; and
flowing said selectively created layer of solder, creating solder balls connecting said discrete electrical component with said conductive plugs in said polymer insulating, separating layer, thereby connecting said discrete electrical component with a pair of points of electrical contact in said layer of passivation. - View Dependent Claims (22, 23, 24, 25, 27, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 71, 72, 73, 74, 75, 81, 82, 85, 86)
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26. A method for mounting a discrete electrical component above the surface of a semiconductor substrate, comprising:
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providing a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;
creating an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;
depositing a passivation layer over said overlaying interconnecting metalization structure;
patterning and etching said layer of passivation, creating openings in said layer of passivation, at least two of said openings overlaying at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure, providing at least one pair of points of electrical contact in said layer of passivation;
selectively creating a layer of solder over the surface of at least one pair of points of electrical contact in said layer of passivation;
positioning said discrete electrical component above and aligned with said selectively created layer of solder such that electrical contact points of said discrete electrical component align with said selectively created layer of solder; and
flowing said layer of selectively created solder, creating solder balls connecting said discrete electrical component with at least one pair of points of electrical contact in said layer of passivation.
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28. An inductor for high performance integrated circuits overlaying the surface of a semiconductor substrate, comprising:
- a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;
an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;
a passivation layer deposited over said overlaying interconnecting metalization structure;
a polymer insulating, separating layer deposited over said passivation layer that is substantially thicker than said passivation layer and that is also substantially thicker than an inter-layer dielectric used for creating said interconnecting metallization structure;
openings formed through said polymer insulating, separating layer and through said passivation layer to expose at least one pair of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure;
said openings filled with a conductive material, creating metal contacts through said openings; and
said inductor formed on the surface of said polymer insulating, separating layer, said inductor being connected to at least one pair of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure.
- a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;
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42. A capacitor for high performance integrated circuits on the surface of a semiconductor substrate, said capacitor comprising a top plate and a bottom plate and a layer of dielectric interspersed between said top and said bottom plate, comprising:
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a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;
an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate, said points of electrical contact provided on the surface of said overlaying interconnecting metalization structure being divided into pairs of even and odd numbered adjacent contact points whereby one point of electrical contact can belong to only one pair;
a passivation layer deposited over said overlaying interconnecting metalization structure;
openings created in said layer of passivation, at least one opening overlaying at least one even contact point of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure;
a first layer of conductive material deposited over the surface of said layer of passivation, including said openings created in said layer of passivation;
an opening created in said first layer of conductive material to at least one of said even numbered points of electrical contact provided in or on the surface of said overlaying interconnecting metalization structure, said first layer of conductive material forming said bottom plate of said capacitor;
a layer of dielectric deposited over the surface of said first layer of conductive material, including said opening to at least one of said even numbered points of electrical contact;
an opening in said layer of dielectric to at least one of said even numbered points of electrical contact, partially exposing at least one of said even numbered points of electrical contact, forming said layer of dielectric interspersed between said top plate and said bottom plate;
a second layer of conductive material deposited over the surface of said layer of dielectric, including at least one opening created in said layer of dielectric; and
said top plate of said capacitor created by patterning and etching said second layer of conductive material. - View Dependent Claims (43, 44, 45, 46, 47, 49, 76)
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48. A resistor for high performance integrated circuits on the surface of a semiconductor substrate, comprising:
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a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;
an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;
a passivation layer deposited over said overlaying interconnecting metalization structure;
openings created in said layer of passivation, at least two of said openings overlaying at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization;
a layer of resistive conducting material deposited over the surface of said layer of passivation, including said openings created in said layer of passivation; and
a layer of conductive material that interconnects at least one pair of said openings created in said layer of passivation, creating said resistor.
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50. A resistor for high performance integrated circuits on the surface of a semiconductor substrate, comprising:
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a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;
an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;
a passivation layer deposited over said overlaying interconnecting metalization structure;
openings created in said layer of passivation, at least two of said openings overlaying and partially exposing at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure;
a polymer insulating, separating layer deposited over the surface of said patterned and etched layer of passivation, including said openings created in said layer of passivation;
at least one pair of openings in said polymer insulating, separating layer that aligns with at least one pair of openings created in said layer of passivation, partially exposing at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure;
a layer of conductive material deposited over the surface of said polymer insulating, separating layer including said openings created in said polymer insulating, separating layer; and
a layer of resistive conducting material that interconnects at least one pair of said openings created in said layer of passivation, creating said resistor. - View Dependent Claims (51, 52, 53, 54, 55, 57, 58, 59, 60, 61, 62, 77, 78)
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56. A discrete electrical component above the surface of a semiconductor substrate, comprising:
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a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;
an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;
a passivation layer deposited over said overlaying interconnecting metalization structure;
openings created in said layer of passivation, at least two of said openings overlaying at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure, providing at least one pair of points of electrical contact in said layer of passivation;
an polymer insulating, separating layer deposited over the surface of said patterned and etched layer of passivation, including said openings created in said layer of passivation;
at least one pair of openings created in said polymer insulating, separating layer that aligns with at least one pair of points of electrical contact provided in said layer of passivation;
a layer of conductive material selectively deposited over the surface of at least one pair of points of electrical contact provided in said layer of passivation, filling said openings created in said polymer insulating, separating layer, creating conductive plugs through said polymer insulating, separating layer, said conductive plugs overlaying at least one pair of points of electrical contact provided in said layer of passivation;
a layer of solder selectively created over the surface of said conductive plugs;
said discrete electrical component positioned above and in alignment with said selectively created layer of solder such that electrical contact points of said discrete electrical component align with said selectively created layer of solder; and
said selectively created layer of solder flowed, creating solder balls connecting said discrete electrical component with said conductive plugs in said polymer insulating, separating layer, thereby connecting said discrete electrical component with a pair of points of electrical contact in said layer of passivation.
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63. A discrete electrical component mounted above the surface of a semiconductor substrate, comprising:
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a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;
an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;
a passivation layer deposited over said overlaying interconnecting metalization structure;
openings created in said layer of passivation, at least two of said openings overlaying at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure, providing at least one pair of points of electrical contact in said layer of passivation;
a layer of solder selectively deposited over the surface of at least one pair of points of electrical contact in said layer of passivation;
said discrete electrical component positioned above and aligned with said selectively deposited layer of solder such that electrical contact points of said discrete electrical component align with said selectively deposited layer of solder; and
said layer of selectively deposited solder flowed, creating solder balls connecting said discrete electrical component with at least one pair of points of electrical contact in said layer of passivation. - View Dependent Claims (64, 65)
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Specification