Embedded debug system using an auxiliary instruction queue
First Claim
1. Apparatus embedded in a processor system comprising:
- an auxiliary instruction queue (IQ) including a plurality of storage registers programmable with a set of instructions; and
control means for governing the programming of said auxiliary IQ with said set of instructions and for controlling insertion of said programmed instructions of said auxiliary IQ into an instruction execution stream of said processor system substantially without interrupting processing operations thereof.
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Accused Products
Abstract
Apparatus embedded in a processor system comprises: an auxiliary instruction queue (IQ); and control circuits for governing the programming of registers of the auxiliary IQ with a set of instructions and for controlling insertion of the programmed instructions of the auxiliary IQ into an instruction execution stream of the processor system substantially without interrupting processing operations thereof. In another embodiment, the IQ is memory mapped to render it part of the memory space of the processor system and the control circuits govern the programming of the auxiliary IQ with a set of debug instructions accessed from a debug monitor program over the bus. In yet another embodiment, each storage register of the IQ is fabricated in the IC to survive an upset transient wherein a monitor circuit detects an onset of the upset transient and governs the control circuits to transfer data of selected registers of the processor system into the auxiliary IQ for storage during the upset transient. A method of protecting the integrated circuit (IC) processor system against an upset transient is also disclosed. In still another embodiment, the registers of the auxiliary IQ are configurable in the power-up mode to store a set of boot loader instructions which are accessible by the processor system.
159 Citations
50 Claims
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1. Apparatus embedded in a processor system comprising:
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an auxiliary instruction queue (IQ) including a plurality of storage registers programmable with a set of instructions; and
control means for governing the programming of said auxiliary IQ with said set of instructions and for controlling insertion of said programmed instructions of said auxiliary IQ into an instruction execution stream of said processor system substantially without interrupting processing operations thereof. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30)
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26. Debug apparatus embedded in a processor system that has a debug monitor program stored in a program memory thereof, said apparatus comprising:
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an auxiliary instruction queue (IQ) including a plurality of storage registers programmable with a set of debug instructions, said auxiliary IQ being coupled to a bus of the processor system, said storage registers being memory mapped to render the auxiliary IQ part of the memory space of the processor system; and
control means for governing the programming of said auxiliary IQ with said set of debug instructions accessed from the debug monitor program over said bus and for controlling insertion of said programmed debug instructions of said auxiliary IQ into an instruction execution stream of said processor system substantially without interrupting processing operations thereof.
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31. Protection apparatus embedded in an integrated circuit (IC) processor system comprising:
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an auxiliary data queue (DQ) including a plurality of storage registers for temporary storage of data, each said storage register being fabricated in the IC to survive an upset transient, said auxiliary DQ being coupled to a bus of the processor system, said storage registers being memory mapped to render the auxiliary DQ part of the memory space of the processor system; and
monitor means for detecting an onset of the upset transient; and
control means governed by said monitor means for transferring data of selected registers of the processor system into registers of said auxiliary DQ for storage during said upset transient. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39)
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40. Method of protecting an integrated circuit (IC) processor system against an upset transient comprising the steps of:
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detecting an onset of the upset transient;
transferring data of selected registers of the processor system into upset transient survivable registers of an auxiliary data queue (DQ) upon said detected onset; and
storing said data in said registers of the auxiliary DQ during the upset transient. - View Dependent Claims (41, 42, 43, 44, 45, 46, 48, 49, 50)
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47. Auxiliary boot loader apparatus embedded in a processor system and operable in a power-up mode of said processor system, said apparatus comprising:
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an auxiliary instruction queue (IQ) including a plurality of storage registers configurable in said power-up mode to store a set of boot loader instructions, said registers of the auxiliary IQ being accessible by the processor system; and
means for detecting said power-up mode and causing said processor system to access and execute the stored instructions of said auxiliary IQ.
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Specification