Method and apparatus for scheduling memory current and temperature calibrations based on queued memory workload

• US 20020065981A1
• Filed: 11/30/2000
• Published: 05/30/2002
• Est. Priority Date: 11/30/2000
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Jenne, John E., Olarig, Sompong P.
• Granted Patent: US 6,631,440 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

A computer system includes a memory controller that controls and formats transactions with a high speed memory. The memory controller includes a read queue, a write queue, and various other queues in which memory transactions may be stored pending execution. The memory controller periodically executes calibration cycles, such as temperature calibration cycles to the memory to reduce memory errors. The temperature calibration cycles may include an idle state during which no read transactions can be executed. The memory controller includes arbitration logic that reduces latency by issuing read transaction first. Once reads have been issued, the arbitration logic executes any pending temperature cycles. During the idle period of the calibration cycle, the arbitration logic schedules write transactions, and transactions to memory from other queues and devices, including precharge transactions, row activate transactions, refresh cycles, and other calibration cycles.

Claims

1. A computer system, comprising:

a CPU;

a memory controller coupled to said CPU, said memory controller including at least one high priority queue and at least one low priority queue, and wherein said memory controller executes calibration cycles to said system memory to re-calibrate said system memory;

a system memory coupled to said memory controller, with said memory controller controlling and formatting transactions to the system memory; and

wherein said memory controller further includes arbitration logic that is capable of prioritizing transactions pending in said high priority queue to execute prior to executing said calibration cycles.

2. The system of claim 1, wherein said memory controller is capable of prioritizing said calibration cycles to execute prior to transactions pending in said low priority queue.

3. The system of claim 2, wherein said memory controller is capable of scheduling the transactions pending in said low priority queue to execute during idle periods in the calibration cycle.

4. The system of claim 3, wherein said high priority queue comprises a read queue, and transactions pending in said read queue execute prior to execution of said calibration cycle.

5. The system of claim 4, wherein said low priority queue comprises a write queue, and wherein said calibration cycle executes prior to transactions pending in said write queue, and wherein said write queues are batched to execute during idle periods in said calibration cycle.

6. The system of claim 5, wherein the calibration cycle comprises a temperature cycle, and said temperature calibration cycles includes an idle period during which no reads can execute.

7. The system of claim 6, wherein said system memory comprises at least one RDRAM device.

8. The system of claim 4, wherein said low priority queue comprises a precharge queue.

9. The system of claim 4, wherein said at least one low priority queue includes one or more of a write queue, a precharge queue, a RAS queue, a refresh queue or a current calibration queue.

10. The system of claim 1, further comprising a temperature calibration queue, and wherein said at least one high priority queue, said at least one low priority queue, and said temperature calibration queue couple to said arbitration logic, and said arbitration logic selects a transaction to execute.

11. The system of claim 10, further comprising a temperature calibration logic coupled to said temperature calibration queue, and wherein said temperature calibration logic transmits a transaction to execute to said temperature calibration queue based on the expiration of a minimum timer value.

12. The system of claim 11, wherein said system memory comprising a plurality of Rambus DRAM devices arranged in a plurality of channels, and wherein said memory controller includes a Rambus controller associated with each of said plurality of channels, and wherein said arbitration logic selects transactions from said high priority queue, said low priority queue, and said temperature calibration queue to execute.

13. The system of claim 11, wherein said at least one high priority queue includes a read queue and wherein said at least one low priority queue includes a write queue, and wherein said arbitration logic gives highest priority to transactions in said read queue.

14. The system of claim 12, wherein said arbitration logic gives priority to said temperature calibration queue over said write queue so that transactions in said temperature calibration queue execute before transactions in said write queue.

15. The system of claim 14, wherein said arbitration logic schedules transactions in said write queue to execute during idle periods in said temperature calibration cycle.

16. The system of claim 15, wherein said at least one low priority queue also includes a refresh queue, and wherein said arbitration logic memory gives priority to said temperature calibration queue over said refresh queue so that transactions in said temperature calibration queue execute before transactions in said refresh queue, and wherein said arbitration logic schedules transactions in said refresh queue to execute during idle periods in said temperature calibration cycle.

17. The system of claim 15, wherein said at least one low priority queue also includes a precharge queue, and wherein said arbitration logic memory gives priority to said temperature calibration queue over said precharge queue so that transactions in said temperature calibration queue execute before transactions in said precharge queue, and wherein said arbitration logic schedules transactions in said precharge queue to execute during idle periods in said temperature calibration cycle.

18. The system of claim 15, wherein said at least one low priority queue also includes a current calibration queue, and wherein said arbitration logic memory gives priority to said temperature calibration queue over said current calibration queue so that transactions in said temperature calibration queue execute before transactions in said current calibration queue, and wherein said arbitration logic schedules transactions in said current calibration queue to execute during idle periods in said temperature calibration cycle.

19. The system of claim 15, wherein said at least one low priority queue also includes a RAS queue, and wherein said arbitration logic memory gives priority to said temperature calibration queue over said RAS queue so that transactions in said temperature calibration queue execute before transactions in said RAS queue, and wherein said arbitration logic schedules transactions in said RAS queue to execute during idle periods in said temperature calibration cycle.

20. The system of claim 1, wherein said system memory includes a plurality of high-speed DRAM memory devices, and said memory controller periodically schedules calibration cycles to said DRAM memory devices based on the status of a timer in said memory controller.

21. A memory controller that controls and formats operations to system memory, comprising:

at least one high priority queue;

at least one low priority queue;

temperature calibration logic that initiates temperature calibration cycles;

arbitration logic coupled to said at least one high priority, said at least one low priority queue, and said temperature calibration logic; and

wherein said arbitration logic prioritizes transactions pending in said high priority queue to execute prior to executing said temperature calibration cycles.

22. The memory controller of claim 21, wherein said arbitration logic prioritizes said calibration cycles to execute prior to transactions pending in said at least one low priority queue.

23. The memory controller of claim 22, wherein said arbitration logic schedules the transactions pending in said low priority queue to execute during idle periods in the calibration cycle.

24. The memory controller of claim 23, wherein said high priority queue comprises a read queue, and transactions pending in said read queue execute prior to execution of said calibration cycle.

25. The memory controller of claim 22, wherein said low priority queue comprises a write queue, and wherein said calibration cycle executes prior to transactions pending in said write queue, and wherein said write queues are batched to execute during idle periods in said calibration cycle.

26. The memory controller of claim 24, wherein the calibration cycle comprises a temperature calibration cycle that includes an idle period during which no reads can execute.

27. The memory controller of claim 21, wherein said memory controller couples to a system memory that includes at least one Rambus DRAM device.

28. The memory controller of claim 24, wherein said low priority queue comprises a precharge queue.

29. The memory controller of claim 21, wherein said at least one low priority queue includes one or more of a write queue, a precharge queue, a RAS queue, a refresh queue or a current calibration queue.

30. The memory controller of claim 21, further comprising a temperature calibration queue that couples between said temperature calibration logic and said arbitration logic.

31. The memory controller of claim 30, wherein said temperature calibration logic includes a timer and said temperature calibration logic transmits a transaction to execute to said temperature calibration queue based on the expiration of the timer.

32. The memory controller of claim 21, wherein said memory controller includes a plurality of Rambus controllers associated with a respective one of a plurality of memory channels, and wherein said arbitration logic selects transactions from said high priority queue, said low priority queue, and said temperature calibration logic to execute.

33. The memory controller of claim 21, wherein said at least one high priority queue includes a read queue and wherein said at least one low priority queue includes a write queue, and wherein said arbitration logic gives highest priority to transactions in said read queue.

34. The system of claim 33, wherein said arbitration logic gives priority to said temperature calibration logic over said write queue so that transactions issuing from said temperature calibration logic execute before transactions in said write queue.

35. The system of claim 34, wherein said arbitration logic schedules transactions in said write queue to execute during idle periods in said temperature calibration cycle.

37. A system as in claim 36, wherein said arbitration logic prioritizes transactions pending in said read queue to execute prior to executing said calibration cycles.

38. The system of claim 36, wherein the calibration cycle comprises a temperature calibration cycle, and said temperature calibration cycles include an idle period during which no reads can execute.

39. The system of claim 36, wherein said system memory comprises at least one RDRAM device.

40. The system of claim 36, wherein said memory controller includes a temperature calibration queue in which calibration cycles are stored pending execution, and wherein said read queue, said write queue, and said temperature calibration queue couple to said arbitration logic, and said arbitration logic selects a transaction to execute.

41. The system of claim 40, further comprising a temperature calibration logic coupled to said temperature calibration queue, and wherein said temperature calibration logic transmits a transaction to execute to said temperature calibration queue based on the expiration of a minimum timer value.

42. The system of claim 41, wherein said system memory comprising a plurality of Rambus DRAM devices arranged in a plurality of channels, and wherein said memory controller includes a Rambus controller associated with each of said plurality of channels, and wherein said arbitration logic selects transactions from said read queue, said write queue, and said temperature calibration queue to execute.

43. The system of claim 36, wherein said memory controller also includes a refresh queue, and wherein said arbitration logic memory gives priority to said calibration cycle over said refresh queue so that calibration cycle transactions execute before transactions in said refresh queue, and wherein said arbitration logic schedules transactions in said refresh queue to execute during idle periods in said calibration cycle.

44. The system of claim 36, wherein said memory controller also includes a precharge queue, and wherein said arbitration logic memory gives priority to said calibration cycle over said precharge queue so that calibrate cycle transactions execute before transactions in said precharge queue, and wherein said arbitration logic schedules transactions in said precharge queue to execute during idle periods in said calibration cycle.

45. The system of claim 40, wherein said memory controller also includes a current calibration queue, and wherein said arbitration logic memory gives priority to said temperature calibration queue over said current calibration queue so that transactions in said temperature calibration queue execute before transactions in said current calibration queue, and wherein said arbitration logic schedules transactions in said current calibration queue to execute during idle periods in said temperature calibration cycle.

36. A computer system, comprising:

a CPU;

a memory controller coupled to said CPU, said memory controller including a read queue and a write queue, and wherein said memory controller executes calibration cycles to said system memory to re-calibrate said system memory;

a system memory coupled to said memory controller, with said memory controller controlling and formatting transactions to the system memory; and

wherein said memory controller further includes arbitration logic that is capable of prioritizing said calibration cycles to execute prior to transactions pending in said write queue, and wherein said memory controller is capable of scheduling the transactions pending in said write queue to execute during idle periods in the calibration cycle.