Method for fabricating thin film transistor including crystalline silicon active layer

• US 20020068392A1
• Filed: 04/04/2001
• Published: 06/06/2002
• Est. Priority Date: 12/01/2000
• Status: Active Grant

• Current Assignee: PT Plus Company Limited
• Original Assignee: PT Plus Company Limited
• Inventors: Joo, Seung Ki, Lee, Seok Woon
• Granted Patent: US 6,548,331 B2
• Time in Patent Office: Days
• US Class Current: 438/166
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

A method for fabricating a TFT including a crystalline silicon active layer is disclosed, in which the metal which induced the crystallization of the active layer is offset from a gate electrode utilizing a mask used to form a lightly doped drain (LDD) region or an offset junction region in the active layer. The TFT includes a silicon active layer crystallized by crystallization inducing metal and a gate electrode, and has an LDD region or an offset junction region formed in the vicinity of the channel region. The method for fabricating the TFT forms a metal offset region without using an additional photoresist forming process, and forms a LDD region by conducting a low density doping in the metal offset region. As a result, a transistor made according to the present invention has low leakage current in its off-state, and has stable electrical characteristics in its on-state.

Claims

1. A method for fabricating a thin film transistor including a silicon active layer crystallized by crystallization inducing metal, a gate electrode, a lightly doped drain (LDD) region or an offset junction region formed in said active layer, wherein said method the step of:

offsetting said crystallization inducing metal from a channel region of said active layer by using a mask used for forming said LDD region or said offset junction region.

2. The method for fabricating a TFT according to claim 1, wherein said crystallization inducing metal is formed with at least one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd and Pt.

3. The method for fabricating a TFT according to claims 1 or 2, wherein said crystallization inducing metal is formed on said active layer to have a thickness of 10 Å

to 200 Å

by sputtering, heating evaporation, solution coating, or chemical vapor deposition (CVD) method.

4. The method for fabricating a TFT according to claim 3, wherein said active layer is crystallized by thermal treatment using a furnace, RTA(rapid thermal annealing), line scan RTA or excimer laser crystallization (ELC) method.

5. The method for fabricating a TFT according to claim 1, wherein said gate electrode is comprised of multiple gate electrodes and an upper gate electrode of said multiple gate electrodes is used as a mask for forming said LDD region or said offset junction region.

6. The method for fabricating a TFT according to claim 1, wherein a photoresist used to form said gate electrode is used as a mask for forming said LDD region or said offset junction region, and said gate electrode is undercut with respect to said photoresist.

7. The method for fabricating a TFT according to claim 1, wherein a photoresist used to form said gate electrode is re-flowed, and said re-flowed photoresist is used as a mask for forming said LDD region or said offset junction region.

8. The method for fabricating a TFT according to claim 1, wherein an anodic oxide layer is formed on said gate electrode, and said anodic oxide layer is used as a mask for forming said LDD region or said offset junction region.

9. The method for fabricating a TFT according to claim 1, further comprising the steps of:

forming an insulation layer on said gate electrode and said active layer;

forming a sidewall around said gate electrode by performing an anisotropic etching on said insulation layer; and

forming said LDD region or said offset junction region using said side wall as a mask.

10. The method for fabricating a TFT according to claim 1, wherein a gate insulation layer being in contact with said gate electrode is patterned to extend outside of said gate electrode, and said gate insulation layer is used as a mask for forming said LDD region or said offset junction region.

11. The method for fabricating a TFT according to claims 9 or 10, wherein said LDD region is formed by a low-density doping with a high energy using said sidewall or said gate insulation layer as a mask.