Method and apparatus for designing integrated circuits and storage medium for storing the method

• US 20020068989A1
• Filed: 10/25/2001
• Published: 06/06/2002
• Est. Priority Date: 10/26/2000
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yamamoto, Arata, Inoue, Ryouhei, Ebisawa, Motoji
• Granted Patent: US 6,539,529 B2
• Time in Patent Office: Days
• US Class Current: 700/121
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

Disclosed are a method and an apparatus for designing an integrated circuit as well as a storage medium for storing the method, whereby repeaters are laid out automatically without overlapping with existing circuit blocks. A set of layout data is input to let the repeaters fully occupy provisionally regions that are free of circuit blocks and ready to accommodate the repeaters Another set of layout data is generated based on the input layout data to calculate locations in which to insert the repeaters within wiring patterns that fail to meet wiring delay requirements. From among the provisionally laid-out repeaters, those that are closest to the calculated positions are selected. Data about connections of the selected repeaters are added to a net list to update the latter. Data about a layout of the unselected repeaters are removed from the layout data in effect after the provisional layout. The updated net list and the layout data with the unselected repeater layout data removed therefrom are used as a basis for generating wiring patterns of the integrated circuit in question.

Claims

1. An integrated circuit designing method comprising the steps of:

firstly inputting layout data for designating a layout of circuit blocks and wiring patterns constituting an integrated circuit on a substrate, the input layout data serving as a basis for generating layout data such as to let delay adjusting circuits fully occupy, on said substrate, regions which are free of said circuit blocks and ready to accommodate said delay adjusting circuits for adjusting wiring delays between said circuit blocks;

secondly designating locations in which to insert said delay adjusting circuits inside wiring patterns which, among the patterns designated by said input layout data, fail to meet predetermined wiring delay requirements, said locations being designated so that said wiring patterns will meet the delay requirements in conjunction with the inserted delay adjusting circuits;

thirdly selecting, from among said delay adjusting circuits designated by said layout data generated in said first step, the delay adjusting circuits that are closest to said locations designated in said second step;

fourthly supplementing data about connections of said circuit blocks in said input layout data with data about connections of the delay adjusting circuits selected in said third step;

fifthly removing from said layout data generated in said first step the data about a circuit layout not included in the connection data supplemented in said fourth step; and

sixthly generating wiring patterns of said integrated circuit based on the connection data supplemented in said fourth step and on the layout data from which the data were removed in said fifth step.

2. An integrated circuit designing apparatus comprising:

layout means for inputting layout data for designating a layout of circuit blocks and wiring patterns constituting an integrated circuit on a substrate, the input layout data serving as a basis for generating layout data such as to let delay adjusting circuits fully occupy, on said substrate, regions which are free of said circuit blocks and ready to accommodate said delay adjusting circuits for adjusting wiring delays between said circuit blocks;

insertion location designating means for designating locations in which to insert said delay adjusting circuits inside wiring patterns which, among the patterns designated by said input layout data, fail to meet predetermined wiring delay requirements, said locations being designated so that said wiring patterns will meet the delay requirements in conjunction with the inserted delay adjusting circuits;

selecting means for selecting, from among said delay adjusting circuits designated by said layout data generated by said layout means, the delay adjusting circuits that are closest to said locations designated by said insertion location designating means;

connection data updating means for supplementing data about connections of said circuit blocks in said input layout data with data about connections of the delay adjusting circuits selected by said selecting means;

layout data updating means for removing from said layout data generated by said layout means the data about a circuit layout not included in the connection data supplemented by said connection data updating means; and

wiring pattern generating means for generating wiring patterns of said integrated circuit based on the connection data supplemented by said connection data updating means and on the layout data from which the data were removed by said layout data updating means.

3. A storage medium which stores a program in a manner readable by a computer, said program comprising the steps of:

firstly inputting layout data for designating a layout of circuit blocks and wiring patterns constituting an integrated circuit on a substrate, the input layout data serving as a basis for generating layout data such as to let delay adjusting circuits fully occupy, on said substrate, regions which are free of said circuit blocks and ready to accommodate said delay adjusting circuits for adjusting wiring delays between said circuit blocks;

secondly designating locations in which to insert said delay adjusting circuits inside wiring patterns which, among the patterns designated by said input layout data, fail to meet predetermined wiring delay requirements, said locations being designated so that said wiring patterns will meet the delay requirements in conjunction with the inserted delay adjusting circuits;

thirdly selecting, from among said delay adjusting circuits designated by said layout data generated in said first step, the delay adjusting circuits that are closest to said locations designated in said second step;

fourthly supplementing data about connections of said circuit blocks in said input layout data with data about connections of the delay adjusting circuits selected in said third step;

fifthly removing from said layout data generated in said first step the data about a circuit layout not included in the connection data supplemented in said fourth step; and

sixthly generating wiring patterns of said integrated circuit based on the connection data supplemented in said fourth step and on the layout data from which the data were removed in said fifth step.