SEMICONDUCTOR MEMORY DEVICE USING DOUBLE LAYERED CAPPINGPATTERN AND SEMICONDUCTOR MEMORY DEVICE FORMED THEREBY

• US 20020070398A1
• Filed: 02/05/2001
• Published: 06/13/2002
• Est. Priority Date: 12/11/2000
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jae-Goo
• Granted Patent: US 6,403,996 B1
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 21/7688 by deposition over sacrificial masking layer, e.g. lift-off lift-off per se H01L21/0272
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A method of forming a semiconductor memory device using a double layered capping pattern and a semiconductor memory device formed thereby are provided. A plurality of interconnection patterns are formed on a semiconductor substrate. Each of the interconnection patterns includes a interconnection line and a double layered capping pattern. The double layered capping pattern includes a first capping pattern and a second capping pattern, which are sequentially stacked. The second capping pattern is formed of a material layer having an etching selectivity with respect to the first capping pattern. A planarized separating layer is formed between the adjacent interconnection patterns. The substrate having the planarized separating layer is covered with a sacrificial layer. The sacrificial layer is formed of a material layer having a wet etching selectivity with respect to the planarized separating layer. The sacrificial layer and the planarized separating layer are patterned to form a hole exposing a predetermined region of the semiconductor substrate. The hole is filled with a conductive pattern. The sacrificial layer is then removed to thereby protrude the conductive pattern. The conductive pattern and the second capping pattern are planarized, thereby forming a conductive plug in the hole and concurrently exposing the first capping pattern.

Claims

1. A method of forming a semiconductor memory device comprising:

forming an inter-layer insulating layer on a semiconductor substrate;

forming a plurality of interconnection patterns on the inter-layer insulating layer, each of the interconnection patterns including an interconnection line, a first capping pattern and a second capping pattern which are sequentially stacked;

forming insulating spacers on sidewalls of the plurality of interconnection patterns;

forming a planarized separating layer on the inter-layer insulating layer between the interconnection patterns;

forming a sacrificial layer on an entire surface of the semiconductor substrate including the planarized separating layer;

patterning the sacrificial layer, the planarized separating layer and the inter-layer insulating layer using the spacers and the interconnection patterns as etch stoppers, thereby forming a hole between the interconnection patterns, exposing a predetermined region of the semiconductor substrate;

forming a conductive pattern filling the hole;

selectively removing the sacrificial layer; and

planarizing the conductive pattern and the second capping patterns, thereby forming a conductive plug in the hole and concurrently exposing the first capping patterns.

2. The method of claim 1, wherein the first capping patterns are formed of an insulating layer having an etching selectivity with respect to the inter-layer insulating layer.

3. The method of claim 1, wherein the second capping patterns are formed of a material layer having an etching selectivity with respect to the sacrificial layer, the planarized separating layer, and the inter-layer insulating layer.

4. The method of claim 3, wherein the material layer comprises a polysilicon layer.

5. The method of claim 1, wherein the spacers are formed of an insulating layer having an etching selectivity with respect to the inter-layer insulating layer.

6. The method of claim 1, wherein forming the planarized separating layer comprises:

forming a separating layer filling gap regions between the interconnection patterns on an entire surface of the semiconductor substrate including the spacers; and

planarizing the separating layer until the second capping patterns are exposed.

7. The method of claim 6, wherein the separating layer is formed of an insulating layer having an etching selectivity with respect to the spacers, the first capping pattern and the second capping pattern.

8. The method of claim 6, wherein the separating layer is formed of a high density plasma (HDP) oxide layer.

9. The method of claim 1, wherein the sacrificial layer is formed of an insulating layer having a wet etching selectivity with respect to the planarized separating layer.

10. The method of claim 1, wherein the sacrificial layer is formed of a material selected from a group of materials consisting of:

borophosphosilicate glass (BPSG) layer, and a spin on glass (SOG) layer.

11. The method of claim 1, wherein forming the conductive pattern comprises:

forming a conductive layer filling the hole on an entire surface of the semiconductor substrate including the hole; and

planarizing the conductive layer until a top surface of the sacrificial layer is exposed.

12. The method of claim 11, wherein the conductive layer is formed of the same material layer as the second capping patterns.

13. The method of claim 1, wherein planarizing the conductive pattern and the second capping patterns is performed using a chemical mechanical polishing (CMP) process.

14. The method of claim 13, wherein the CMP process is performed using the first capping patterns as CMP stoppers.

16. The method of claim 15, wherein forming the inter-layer insulating layer is preceded by:

providing the semiconductor substrate;

forming a plurality of word line patterns and a plurality of gate patterns on the semiconductor substrate in the cell region and on the semiconductor substrate in the peripheral region respectively, each of the word line patterns including a word line, a first capping pattern and a second capping pattern which are sequentially stacked and each of the gate patterns including a gate electrode, a first capping pattern and a second capping pattern which are sequentially stacked;

forming gate spacers on sidewalls of the word line patterns and the gate patterns;

forming a planarized lower separating layer on the semiconductor substrate between the word line patterns and between the gate patterns;

forming a lower sacrificial layer on an entire surface of the semiconductor substrate including the planarized lower separating layer;

patterning the lower sacrificial layer and the planarized lower separating layer using the word line patterns, the gate patterns and the gate spacers as etch stoppers, thereby forming a storage node pad hole exposing a source region of the cell transistor and concurrently forming a bit line pad hole exposing a drain region of the cell transistor;

forming lower conductive patterns filling the storage node pad hole and the bit line pad hole;

selectively removing the lower sacrificial layer; and

planarizing the lower conductive patterns and the second capping patterns of the word line patterns, thereby forming a storage node pad and a bit line pad in the storage node pad hole and in the bit line pad hole respectively and concurrently exposing the first capping patterns of the word line patterns.

17. The method of claim 16, wherein the second capping patterns of the word line patterns and the gate patterns are formed of a silicon layer.

18. The method of claim 15, wherein forming the planarized upper separating layer comprises:

forming an upper separating layer filling gap regions between the bit line patterns on an entire surface of the semiconductor substrate including the bit line spacers; and

planarizing the upper separating layer until the second capping patterns of the bit line patterns are exposed.

19. The method of claim 18, wherein planarizing the upper separating layer is performed so that the second capping pattern extensions in the peripheral region are covered with the planarized upper separating layer.

20. The method of claim 18, wherein planarizing the upper separating layer is performed using a CMP process.

21. The method of claim 20, wherein the CMP process is performed using the first capping patterns in the cell array region as CMP stoppers.

22. The method of claim 15, wherein the planarized upper separating layer is formed of a high density plasma (HDP) oxide layer.

23. The method of claim 15, wherein the upper sacrificial layer is formed of a borophosphosilicate glass (BPSG) layer or a spin on glass (SOG) layer.

24. The method of claim 15, wherein the second capping pattern extensions in the peripheral region are covered with the planarized upper separating layer following planarizing the upper conductive pattern and the second capping patterns in the cell array region.

26. The semiconductor device of claim 25 wherein the second capping layer comprises a material having etch selectivity with respect to the first capping layer.

27. The semiconductor device of claim 26 wherein the second capping layer material is a conductive material.

28. The semiconductor device of claim 27 wherein the second capping layer comprises polysilicon.

29. The semiconductor device of claim 25 wherein the device is adjacent to a region in which a self-aligning contact is formed through the second insulating layer.

30. The semiconductor device of claim 25 wherein the first capping layer comprises silicon nitride.

15. A method of forming a semiconductor memory device including a cell array region having a plurality of cell transistors and a peripheral region having a plurality of sense amplifier transistors, comprising:

forming an inter-layer insulating layer on a semiconductor substrate;

forming a plurality of bit line patterns and a plurality of bit line pattern extensions on the inter-layer insulating layer in the cell array region and on the inter-layer insulating layer in the peripheral region respectively, each of the bit line patterns including a bit line, a first capping pattern and a second capping pattern which are sequentially stacked and each of the bit line pattern extensions including a bit line extension, a first capping pattern extension and a second capping pattern extension which are sequentially stacked;

forming bit line spacers on sidewalls of the bit line patterns and the bit line pattern extensions;

forming a planarized upper separating layer on the semiconductor substrate including the bit line spacers;

forming an upper sacrificial layer on the semiconductor substrate including the planarized upper separating layer;

patterning the upper sacrificial layer, the planarized upper separating layer and the inter-layer insulating layer using the bit line spacers and the bit line patterns as etch stoppers, thereby forming at least one storage node plug hole exposing a predetermined region of the semiconductor substrate in the cell region;

forming an upper conductive pattern filling the storage node plug hole;

selectively removing the upper sacrificial layer; and

planarizing the upper conductive pattern and the second capping patterns, thereby forming a storage node plug in the storage node plug hole and concurrently exposing the first capping patterns in the cell array region.

25. A semiconductor device comprising:

a first insulating layer formed on a semiconductor substrate; and

a conducting line formed on the first insulating layer including a conductor and a capping layer formed over the conductor, the capping layer comprising a first capping layer, and a second capping layer formed over the first capping layer

a second insulating layer formed on the first insulating layer and on the first and second capping layers, the first and second capping layers having etch selectivity with respect to the second insulating layer.

31. A method of forming a semiconductor device comprising:

forming a first insulating layer over a semiconductor substrate;

forming a patterned stack comprising a conducting line, a first capping layer and a second capping layer on the first insulating layer;

forming a second insulating layer over the first insulating layer and over the patterned stack;

wherein the first and second capping layers have etching selectivity with respect to the second insulating layer.

32. The method of claim 31 wherein the second capping layer comprises a material having etch selectivity with respect to the first capping layer.

33. The method of claim 31 wherein the second capping layer material is a conductive material.

34. The method of claim 33 wherein the second capping layer comprises polysilicon.

35. The method of claim 31 further comprising forming a self-aligning contact structure adjacent to the semiconductor device.

36. The method of claim 31 wherein the first capping layer comprises silicon nitride.

38. The semiconductor memory device of claim 37 wherein the second capping layer comprises a material having etch selectivity with respect to the first capping layer.

39. The semiconductor memory device of claim 37 wherein the second capping layer material is a conductive material.

40. The semiconductor memory device of claim 37 wherein the second capping layer comprises polysilicon.

41. The semiconductor memory device of claim 37 wherein the first capping layer comprises silicon nitride.

42. The semiconductor memory device of claim 37, wherin the second insulating layer is a planarized layer that covers the second conductor.

43. The semiconductor memory device of claim 37, wherein one of the first and second conductors is a bit line.

44. The semiconductor memory device of claim 37 further comprising a sacrificial layer formed on the second insulating layer.

45. The semiconductor memory device of claim 44 wherein the sacrificial layer comprises a material layer having a wet etching selectivity with respect to the second insulating layer.

46. The semiconductor memory device of claim 37, wherein the second insulating layer is a high-density plasma oxide layer.

48. The method of claim 47 wherein the separating layer comprises a material selected from the group of materials consisting of high-temperature oxide (HTO) and high-density plasma (HDP).

49. The method of claim 47 wherein following planarizing at least a portion of the second capping layers on a subset of the patterned stacks are covered by the separating layer.

50. The method of claim 47 wherein the sacrificial layer has a wet-etching rate that is faster than that of the separating layer.

51. The method of claim 47 wherin the sacrificial layer comprises a material selected from the group of materials consisting of silicon oxide containing impurities and spin on glass (SOG).

52. The method of claim 47 wherein forming conductive plugs comprises forming a conductive layer in holes formed through the sacrificial layer, the separating layer, and the insulating layer, and etching the conductive layer until a top surface of the sacrificial layer is exposed.

53. The method of claim 47 further comprising planarizing the conductive plugs, wherein during the planarizing of the plugs, the capping layer is removed on a subset of the patterned stacks.

37. A semiconductor memory device including a cell array region and a peripheral region, comprising:

a first insulating layer formed over a semiconductor substrate;

a first conductive pattern formed over the first insulating layer in the cell array region, the first conductive pattern including a first conductive line and a first capping layer which are sequentially stacked;

a second conductive pattern formed over the first insulating layer in the peripheral region, the second conductive pattern including a second conductive line, a first capping layer and a second capping layer which are sequentially stacked; and

a second insulating layer formed over the first insulating layer, and the first and second conductive patterns;

the first and second capping layers having etch selectivity with respect to the second insulating layer.

47. A method for forming a semiconductor device comprising:

forming an insulating layer over a semiconductor substrate;

forming a plurality of patterned stacks, each comprising a conducting line, a first capping layer and a second capping layer on the insulating layer;

forming a separating layer over the insulating layer and over the patterned stack;

wherein the first and second capping layers have etching selectivity with respect to the separating layer;

planarizing the separating layer until the second capping layer is exposed;

forming a sacrificial layer over the planarized separating layer;

forming conductive plugs through the sacrificial layer, the planarized separating layer, and the insulating layer.