Semiconductor device having a marking recess and method of manufacturing the same

• US 20020072195A1
• Filed: 06/28/2001
• Published: 06/13/2002
• Est. Priority Date: 12/12/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Anma, Masatoshi, Ooto, Kenichi
• Granted Patent: US 6,599,809 B2
• Time in Patent Office: Days
• US Class Current: 438/401
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device capable of preventing yield reduction and a method of manufacturing the same can be obtained. The method of manufacturing a semiconductor device including an element formation region arranged on a semiconductor substrate and an external region arranged on the semiconductor substrate and surrounding the element formation region, includes the steps of: providing the external region with an interlayer insulating film having a marking recess; providing a covering film extending from an internal portion of the marking recess to an upper surface of the interlayer insulating film; providing a filling film located on the covering film and filling at least the marking recess; and chemically mechanically polishing and moving the covering film on an upper surface of the interlayer insulating film, with the filing film filling at least the marking recess.

Claims

1. A method of manufacturing a semiconductor device including an element formation region arranged on a semiconductor substrate and an external region arranged on said semiconductor substrate and surrounding said element formation region, comprising the steps of:

providing in said external region an interlayer insulating film having a marking recess;

providing a covering film extending from an internal portion of said marking recess to an upper surface of said interlayer insulating film;

providing a filling film located on said covering film and filling at least said marking recess; and

with said filling film filling at least said marking recess, chemically mechanically polishing and thus removing said covering film located on said upper surface of said interlayer insulating film.

2. The method according to claim 1, wherein said step of providing said filling film includes providing a resin film in said marking recess.

3. The method according to claim 1, wherein said step of providing said filling film includes filling said marking recess with a spin-on-glass film.

4. The method according to claim 1, wherein:

said step of providing said filling film includes filling said marking recess with an optically opaque film; and

said step of removing said covering film is followed by the step of partially removing said optically opaque film from an upper portion of said marking recess.

5. The method according to claim 4, wherein said optically opaque film is a film formed through a spin-on-glass process and being mixed with a dopant to be opaque.

6. The method according to claim 1, wherein said step of providing said filling film includes providing a phosphorus-containing, silicon oxide film in said marking recess.

7. The method according to claim 1, wherein said step of removing said covering film is followed by the step of removing an upper surface layer of said interlayer insulating film to allow said covering film in said marking recess to have a portion protruding as seen from an upper surface of said interlayer insulating film.

8. The method according to claim 1, wherein said step of providing said interlayer insulating film includes the steps of:

providing an underlying interlayer insulating film in said external region;

providing an overlying interlayer insulating film on said underlying interlayer insulating film; and

partially removing said overlying and underlying interlayer insulating films to form said marking recess.

9. The method according to claim 1, wherein:

said step of providing said interlayer insulating film includes providing said interlayer insulating film extending to said element formation region;

said step of providing said covering film is provided following the step of providing in said element formation region at said interlayer insulating film a recess smaller in width than said marking recess; and

said step of providing said covering film includes filling said recess with said covering film.

10. The method according to claim 1, wherein said marking recess is used to form at least one selected from the group consisting of an alignment mark and a process management pattern.

11. A semiconductor device manufactured in the method of manufacturing a semiconductor device, as recited in claim 1.

12. A semiconductor device including an element formation region arranged on a semiconductor substrate and an external region arranged on said semiconductor substrate and surrounding said element formation region, comprising:

an interlayer insulating film provided in said external region and having a marking recess; and

an optically opaque film arranged at a bottom of said marking recess.

13. A semiconductor device including an element formation region provided on a semiconductor substrate and an external region arranged on said semiconductor substrate and surrounding said element formation region, comprising:

an interlayer insulating film located in said external region, having an upper surface and provided with a marking recess having a sidewall; and

a covering film provided on said sidewall of said marking recess and partially protruding as seen from said upper surface of said interlayer insulating film.