Transactional memory for distributed shared memory multi-processor computer systems

• US 20020073071A1
• Filed: 10/12/2001
• Published: 06/13/2002
• Est. Priority Date: 02/26/1999
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Pong, Fong, Nguyen, Tung, Russell, Lance
• Granted Patent: US 6,880,045 B2
• Time in Patent Office: Days
• US Class Current: 707/1
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: Y10S 707/99952 Coherency, e.g. same view to multiple users

Abstract

A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.

Claims

1. A multi-processor computer system comprising:

a plurality of processors;

a plurality of caches, each of said plurality of caches operatively connected to one of said plurality of processors;

a first system control unit operatively associated with one of said plurality of processors and operatively connected to one of said plurality of caches, said system control unit having a cache flushing engine operatively connected to said one of said plurality of caches;

a second system control unit operatively associated with said first system control unit and operatively connected to said cache flushing engine;

a memory operatively connected to said second system control unit; and

said first system control unit responsive to an update of one of said caches associated therewith to flush said update to said second system control unit and assure said update is entered into said memory.

2. The multi-processor computer system as claimed in claim 1 including:

a temporary buffer operatively connected through said second system control unit to said memory and to said one of said plurality of caches;

said temporary buffer for containing said update flushed from said one of said plurality of caches; and

said temporary buffer for transferring said update to said memory.

3. The multi-processor computer system as claimed in claim 1 including:

a temporary buffer operatively connected through said second system control unit to said memory and to said one of said plurality of caches;

said memory for receiving said update; and

said temporary buffer for containing data from said memory when said memory receives said update.

4. The multi-processor computer system as claimed in claim 1 including:

a memory operatively connected to said first system control unit;

a temporary buffer operatively connected to said first system control unit;

a temporary buffer operatively connected through said second system control unit to said memory and to said one of said plurality of caches;

said second system control unit operatively connected to another of said plurality of caches;

said second control unit having a cache flushing engine operatively connected to said another of said plurality of caches and operatively connected to said first control unit.

5. The multi-processor computer system as claimed in claim 1 including:

a temporary buffer operatively connected through said second system control unit to said memory and to said one of said plurality of caches;

said cache flushing engine is operatively connected through said second system control unit to said temporary buffer.

6. The multi-processor computer system as claimed in claim 1 including:

a temporary buffer operatively connected through said second system control unit to said memory and to said one of said plurality of caches;

said cache flushing engine is operatively connected through said second system control unit to said memory and said one of said plurality of caches is connected to said memory.