Dual-L2 processor subsystem architecture for networking system

• US 20020073280A1
• Filed: 12/07/2000
• Published: 06/13/2002
• Est. Priority Date: 12/07/2000
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Ng, Alvan Wing
• Granted Patent: US 6,751,704 B2
• Time in Patent Office: Days
• US Class Current: 711/120
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches

Abstract

A method for providing a memory scheme in computer architectures in an efficient and cost effective manner. A processor is configured with access to dual-L2 caches, preferably configured to cache program instructions and data in one cache and shared data in another cache. In one embodiment of the present invention, one L2 cache is accessible to networking interface devices. Optionally, the cache accessible by the networking interface devices is configured as networking buffers, providing cache for packet data being sent within a network. By use of this invention, the packet forwarding speeds in a conventional computer architecture may be increased.

Claims

1. A computer memory architecture for providing cache memory to one or more processors, the architecture comprising:

one or more processors; and

at least two Level 2 caches connected via a bus to the one or more processors for enabling at least one of the one or more processors to store and retrieve data in the at least two Level 2 caches.

2. The computer memory architecture of claim 1, wherein at least one of the at least two Level 2 caches is configured as an L2 Program Cache comprising:

a shared program code space; and

an exclusive program data space and stack.

3. The computer memory architecture of claim 1, wherein at least one of the at least two Level 2 caches is configured as an L2 Packet Cache comprising:

shared control data and descriptors; and

a shared packet data buffer.

4. The computer memory architecture of claim 1, further comprising one or more networking interface devices connected via an I/O bridge to the one or more processors and the at least two Level 2 caches for enabling the one or more networking interface devices to store and retrieve data in at least one of the at least two Level 2 caches.

5. A computer memory architecture for providing cache memory to one or more processors and one or more networking interface devices, the architecture comprising:

one or more processors;

one or more networking interface devices connected via an I/O bridge to the one or more processors;

a first Level 2 cache connected via a bus to the one or more processors for enabling at least one of the one or more processors to store data to and retrieve data from in the first Level 2 cache, and connected via an I/O bridge to the one or more networking interface devices for enabling the one or more networking interface devices to store data to and retrieve data from the first Level 2 cache; and

a second Level 2 cache connected via a bus to the one or more processors for enabling at least one of the one or more processors to store data to and retrieve data from the second Level 2 cache, and connected via an I/O bridge to the one or more networking interface devices for enabling the one or more networking interface devices to store data to and retrieve data from the second Level 2 cache.

6. The computer memory architecture of claim 5, wherein the first Level 2 cache is configured as an L2 Program Cache comprising:

a shared program code space; and

an exclusive program data space and stack.

7. The computer memory architecture of claim 5, wherein the second Level 2 cache is configured as an L2 Packet Cache comprising:

shared control data and descriptors; and

a shared packet data buffer.

8. A method for providing cache memory to one or more processors, the method comprising the steps of:

one or more processors; and

connecting two or more Level 2 caches via a bus to the one or more processors for storing and retrieving data by at least one of the one or more processors.

9. The method of claim 8, wherein at least one of the two or more Level 2 caches is configured as an L2 Program Cache comprising:

a shared program code space; and

an exclusive program data space and stack.

10. The method of claim 8, wherein at least one of the two or more Level 2 caches is configured as an L2 Packet Cache comprising:

shared control data and descriptors; and

a shared packet data buffer.

11. A method for providing cache memory to one or more processors and one or more networking interface devices, the method comprising the steps of:

connecting two or more Level 2 caches to at least one of the one or more processors for enabling the one or more processors to store data to and retrieve data from the two or more Level 2 caches; and

connecting at least one of the two or more Level 2 caches to at least one of the one or more networking interface devices for enabling the one or more networking interface devices to store data to and retrieve data from the two or more Level 2 caches.

12. The method of claim 11, further comprising the step of configuring at least one of the two or more Level 2 caches as an L2 Program Cache comprising:

a shared program code space; and

an exclusive program data space and stack.

13. The method of claim 11, further comprising the step of configuring at least one of the two or more Level 2 caches as an L2 Packet Cache comprising:

shared control data and descriptors; and

a shared packet data buffer.

14. The method of claim 11, wherein at least one of the two or more Level 2 caches is configured as an L2 Packet Cache accessible to at least one of the one or more processors and to at least one of the one or more networking interface devices, the L2 Packet Cache comprising:

shared control data and descriptors; and

a shared packet data buffer.

16. The method of claim 15, wherein the L2 Program Cache comprises:

a shared program code space; and

an exclusive program data space and stack.

17. The method of claim 15, wherein the L2 Packet Cache comprises:

shared control data and descriptors; and

a shared packet data buffer.

18. The method of claim 15, further comprising the steps of:

providing the at least one of the processors with access to the L2 Program Cache;

providing at least one of the one or more processors with access to the L2 Packet Cache; and

providing at least one of the one or more networking interface devices with access to the L2 Packet Cache.

20. The method of claim 19, wherein the upper size limit is 64 bytes.

15. A method for providing cache memory to one or more processors and one or more networking interface devices, the method comprising the steps of:

providing two or more Level 2 caches;

configuring at least one of the two or more Level 2 caches as an L2 Program Cache for storing data comprising data stored in a shared memory;

configuring at least one of the two or more Level 2 caches as an L2 Packet Cache for storing data comprising data stored in a shared memory;

providing access to at least one of the two or more Level 2 caches by at least one of the one or more processors for retrieving data from and storing data to the at least one of the two or more Level 2 caches; and

providing access to at least one of the two or more Level 2 caches by at least one of the one or more networking interface devices for retrieving data from and storing data to the at least one of the two or more Level 2 caches.

19. A method for configuring cache memory to provide access to packet data by one or more processors and one or more networking interface devices, the method comprising the steps of:

configuring a Level 2 cache to comprise one or more buffers, the buffers having an upper size limit;

providing access to the Level 2 cache by the processor for accessing the packet data;

providing access to the Level 2 cache by the networking interface device for accessing the packet data;

storing the packet data in the Level 2 cache if the size of the packet data does not exceed the upper size limit; and

storing the packet data in the Level 2 cache and a main memory if the size of the packet data exceeds the upper size limit.

21. A method for configuring cache memory to provide access to packet headers by one or more processors and one or more networking interface devices, the method comprising the steps of:

configuring a Level 2 cache to comprise one or more buffers, each of the one or more buffers having a size sufficient to store the packet header;

storing the packet header in the Level 2 cache;

providing access to the Level 2 cache by at least one of the one or more processors for retrieving the packet header; and

providing access to the Level 2 cache by at least one of the one or more networking interface devices for retrieving the packet header.