Data processor and data processing system

• US 20020073352A1
• Filed: 11/27/2001
• Published: 06/13/2002
• Est. Priority Date: 11/29/2000
• Status: Active Grant

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Matsui, Shigezumi, Kiuchi, Atsushi, Okubo, Haruyasu
• Granted Patent: US 7,000,140 B2
• Time in Patent Office: Days
• US Class Current: 713/600
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

This data processor can satisfy both requests of a fast transition from a low power consumption state to an operating state and low power consumption, and a data processor has a program running state, a standby mode, a light standby mode, and a sleep mode. In the sleep mode, the supply of a synchronizing clock signal to a central processing unit (CPU) is stopped and the synchronizing clock signal is supplied to other circuit modules. In the standby mode, the frequency multiplication and frequency operation of a clock pulse generator are suspended and the supply of the synchronizing clock signal to the CPU and other circuit modules is stopped. In the light standby mode, the frequency multiplication and frequency division operation of the clock pulse generator are enabled and the supply of the synchronizing clock signal to the CPU and other circuit modules is stopped. In the light standby mode, the transition of the CPU to an instruction executable state is faster than in the standby mode and the lower power consumption than in the sleep mode is obtained.

Claims

1. A data processor, comprising:

a central processing unit which is capable of executing an instruction;

a clock pulse generator that enables frequency multiplication and frequency division operation to a clock signal and is capable of outputting a synchronizing clock signal; and

other circuit modules in a semiconductor chip, and including a standby mode, a light standby mode, and a sleep mode, wherein

in the sleep mode, the supply of the synchronizing clock signal to the central processing unit is stopped and the synchronizing clock signal is supplied to other circuit modules;

in the standby mode, the frequency multiplication and frequency division operation in the clock pulse generator are suspended and the supply of the synchronizing clock signal to the central processing unit and other circuit modules is stopped; and

in the light standby mode, the frequency multiplication and frequency division operation in the clock panel generator are enabled and the supply of the synchronizing clock signal to other circuit modules is stopped.

2. The data processor according to claim 1, further comprising at least a mode control circuit as other circuit modules, wherein this mode control circuit has a control register, sets the sleep mode in response to a first state of the control register when a predetermined instruction is executed by the central processing unit, sets the light standby mode in response to a second state of the control register when the predetermined instruction is executed by the central processing unit, and sets the standby mode in response to a third state of the control register when the predetermined instruction is executed by the central processing unit.

3. The data processor according to claim 2, wherein the mode control circuit is capable of resetting the sleep mode in response to an interrupt request and moving the central processing unit to an instruction executable state.

4. The data processor according to claim 2, wherein the mode control circuit is capable of resetting the light standby mode in response to an external interrupt request and moving the central processing unit to an instruction executable state.

5. The data processor according to claim 2, wherein the mode control circuit is capable of resetting the standby mode in response to an external interrupt request and moving the central processing unit to an instruction executable state.

6. The data processor according to claim 2, wherein the mode control circuit is capable of moving from the sleep mode to the light standby mode in response to counting of up to a predetermined value by a timer that is one of other circuit modules.

7. The data processor according to claim 6, wherein the mode control circuit is capable of suppressing the counting in response to a direct memory access transfer request on the way to the counting of up to the predetermined value by the timer.

8. The data processor according to claim 2, wherein the mode control circuit controls the stop of supplying a synchronizing clock signal to the central processing unit in the sleep mode by the suppression of input operation in a clock input circuit of the central processing unit.

9. The data processor according to claim 2, wherein the mode control circuit controls the stop of supplying a synchronizing clock signal to the central processing unit and other circuits in the light standby mode by the suppression of output operation in a clock output circuit of a clock pulse generator.

10. The data processor according to claim 1, wherein the clock pulse generator comprises a PLL circuit that multiplies a frequency of the clock signal and a frequency divider that frequency-divides a cycle of the clock signal.

11. The data processor according to claim 10, wherein the clock pulse generator comprises the PLL circuit that multiplies the frequency of the clock signal and the frequency divider that frequency-divides the cycle of the clock signal.

13. The data processor according to claim 12, wherein the predetermined lapse of time is obtained by counting operation of up to a predetermined value by a timer that is one of other circuit modules.

14. The data processor according to claim 13, further comprising a direct memory access controller as one of other circuit modules, wherein the timer initializes a counted value in response to a direct memory access transfer request to the direct memory access controller on the way to the counting operation of up to the predetermined value.

15. The data processor according to claim 12, wherein the mode control circuit comprises a control register, and sets the first mode in response to a first state of the control register when a predetermined instruction is executed by the central processing unit and sets the second mode in response to a second state of the control register when the predetermined instruction is executed by the central processing unit.

16. The data processor according to claim 15, wherein the mode control circuit resets the first mode in response to an interrupt request and moves the central processing unit to an instruction executable state.

17. The data processor according to claim 15, wherein the mode control circuit resets the second mode in response to an external interrupt request and moves the central processing unit to an instruction executable state.

18. The data processor according to claim 12, wherein the mode control circuit is capable of controlling the stop of supplying the synchronizing clock signal to the central processing unit in the sleep mode by the suppression of input operation in a clock input circuit of the central processing unit.

19. The data processor according to claim 12, wherein the mode control circuit controls the stop of supplying the synchronizing clock signal to the central processing unit and other circuits in the light standby mode by the suppression of output operation in a clock output circuit of the clock pulse generator.

20. The data processor according to claim 15, wherein the mode control circuit controls the stop of supplying the synchronizing clock signal to the central processing unit and other circuits in the sleep standby mode by the suppression of the output operation in the clock input circuit of the central processing unit.

21. The data processor according to claim 15, wherein the mode control circuit controls the stop of supplying the synchronizing clock signal to the central processing unit and other circuits in the light standby mode by the suppression of the output operation in the clock output circuit of the clock pulse generator.

22. The data processor according to claim 12, wherein the clock pulse generator comprises a phase-locked loop circuit that multiplies a frequency of the clock signal and a frequency divider that frequency-divides a cycle of the clock signal.

23. The data processor according to claim 15, wherein the clock pulse generator comprises a phase-locked loop circuit that multiplies a frequency of a clock signal and a frequency divider that frequency-divides a cycle of the clock signal.

25. The data processing system according to claim 24, wherein a battery power supply uses an operating power supply.

26. A data processing system, comprising:

the data processor according to claim 15;

a memory that the central processing unit of the data processor can access; and

a circuit that requests an interrupt from the data processor.

12. A data processor, comprising:

a central processing unit that can execute an instruction;

a clock pulse generator that enables frequency multiplication and frequency operation to a clock signal and outputs a synchronizing clock signal; and

other circuit modules in a semiconductor chip, and including a mode control circuit that controls settings of at least first and second modes as other circuit modules, wherein

in the first mode, the supply of the synchronizing clock signal to the central processing unit is stopped and the synchronizing clock signal is supplied to other circuit modules;

in the second mode, the frequency multiplication and frequency division operation in the clock pulse generator are suspended and the supply of the synchronizing clock signal to the central processing unit and other circuit modules is stopped; and

in the light standby mode, the frequency multiplication and frequency division operation in the clock pulse generator are enabled and the supply of the synchronizing clock signal to other circuit modules is stopped, and

the mode control circuit moves the first operation mode to the second operation mode when there is no operation instruction to the central processing unit until a predetermined lapse of time after the first mode is set.

24. A data processing system, comprising:

the data processor according to claim 12;

a memory that the central processing unit of the data processor can access; and

a circuit that requests an interrupt from the data processor.