Block based design methodology with programmable components

• US 20020073380A1
• Filed: 03/19/2001
• Published: 06/13/2002
• Est. Priority Date: 09/30/1998
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Cooke, Laurence H., Venkatramani, Kumar, Shyr, Jin-Sheng
• Granted Patent: US 6,968,514 B2
• Time in Patent Office: Days
• US Class Current: 716/1
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A method for designing a circuit block includes the steps of selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, at least one of said circuit blocks being programmable; collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer'"'"'s experience being adaptable to a processing method; accepting or rejecting a design of the circuit system in a manner based on the designer'"'"'s experience data and acceptable degree of risk; upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks (FEA); and, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, in compliance with the criteria and modified constraints without changing the selected circuit block and the processing method.

Claims

1. A method for designing a circuit block, comprising the steps of:

(a) selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, at least one of said circuit blocks being programmable;

(b) collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer'"'"'s experience being adaptable to a processing method;

(c) accepting or rejecting a design of the circuit system in a manner based on the designer'"'"'s experience data and acceptable degree of risk;

(d) upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks (FEA); and

(e) upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, in compliance with the criteria and modified constraints without changing the selected circuit block and the processing method.