Method for specifying, identifying, selecting or verifying differential signal pairs on IC packages

• US 20020073384A1
• Filed: 12/11/2000
• Published: 06/13/2002
• Est. Priority Date: 12/11/2000
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Lussier, Craig, Natonio, Joseph, Buffet, Patrick H.
• Granted Patent: US 6,606,732 B2
• Time in Patent Office: Days
• US Class Current: 716/4
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

An automated method of selecting differential pairs in an integrated circuit comprising loading the design database for the integrated circuit package, and selecting output parameters for the differential pairs comprises adjacency criteria for the different pairs, time of flight tolerances for the differential pairs, and the redistribution layers and their voltage references. The method then includes comparing the output parameters to the design in the design database, and obtaining a resulting differential pairs list. The differential pair list preferably includes differential signal pairs having electrical characteristics within a predetermined design tolerance range. At least some of the differential signal pairs may comprise individual wires or connectors not physically adjacent one another.

Claims

1. An automated method of selecting differential pairs in an integrated circuit comprising:

loading the design database for the integrated circuit package;

selecting output parameters for the differential pairs comprising;

adjacency criteria for the different pairs,

time of flight tolerances for the differential pairs, and

the redistribution layers and their voltage references;

comparing the output parameters to the design in the design database;

obtaining a resulting differential pairs list.

2. The method of claim 1 wherein the differential pair list includes differential signal pairs having electrical characteristics within a predetermined design tolerance range.

3. The method of claim 2 wherein at least some of the differential signal pairs comprise individual wires or connectors not physically adjacent one another.

4. The method of claim 2 wherein the differential pair list includes bundles of differential signal pairs having electrical characteristics within a predetermined design tolerance range.

5. The method of claim 4 wherein at least some of the differential signal pairs in the bundles are differential signal pairs not physically adjacent one another.

6. The method of claim 4 wherein the differential pair list includes groups of differential signal pairs having electrical characteristics within a predetermined design tolerance range.

7. The method of claim 6 wherein at least some of the differential signal pairs are in the groups are bundles of differential signal pairs not physically adjacent one another.

8. The method of claim 1 further including obtaining a table of resistance, inductance and capacitance values of each differential signal pair.

9. An automated method of selecting differential pairs in an integrated circuit, at least some of the differential signal pairs comprising individual wires or connectors not physically adjacent one another, the method comprising:

loading the design database for the integrated circuit package;

selecting output parameters for the differential pairs comprising;

adjacency criteria for the different pairs,

time of flight tolerances for the differential pairs, and

the redistribution layers and their voltage references;

comparing the output parameters to the design in the design database;

obtaining a resulting differential pairs list, the differential pair list including differential signal pairs having electrical characteristics within a predetermined design tolerance range.

10. The method of claim 9 wherein the differential pair list includes bundles of differential signal pairs having electrical characteristics within a predetermined design tolerance range.

11. The method of claim 10 wherein at least some of the differential signal pairs in the bundles are differential signal pairs not physically adjacent one another.

12. The method of claim 9 wherein the differential pair list includes groups of differential signal pairs having electrical characteristics within a predetermined design tolerance range.

13. The method of claim 12 wherein at least some of the differential signal pairs are in the groups are bundles of differential signal pairs not physically adjacent one another.

14. The method of claim 9 further including obtaining a table of resistance, inductance and capacitance values of each differential signal pair

15. An article of manufacture comprising a computer usable medium having computer readable program code means embodied therein for selecting differential pairs in an integrated circuit, said article comprising:

computer readable program code means for loading the design database for the integrated circuit package;

computer readable program code means for selecting output parameters for the differential pairs comprising adjacency criteria for the different pairs, time of flight tolerances for the differential pairs, and the redistribution layers and their voltage references;

computer readable program code means for comparing the output parameters to the design in the design database; and

computer readable program code means for obtaining a resulting differential pairs list.

16. A system for selecting differential pairs in an integrated circuit comprising:

means for loading the design database for the integrated circuit package;

means for selecting output parameters for the differential pairs comprising adjacency criteria for the different pairs, time of flight tolerances for the differential pairs, and the redistribution layers and their voltage references;

means for comparing the output parameters to the design in the design database; and

means for obtaining a resulting differential pairs list.

17. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for selecting differential pairs in an integrated circuit, said method steps comprising:

loading the design database for the integrated circuit package;

selecting output parameters for the differential pairs comprising;

adjacency criteria for the different pairs,

time of flight tolerances for the differential pairs, and

the redistribution layers and their voltage references;

comparing the output parameters to the design in the design database; and

obtaining a resulting differential pairs list.