Semiconductor device and a method of manufacturing the same
First Claim
1. A semiconductor device comprising:
- a plurality of nonvolatile memory cells arranged on a semiconductor substrate in matrix form, each including, a gate insulating film covering a channel region in a main surface of the semiconductor substrate of a first conductivity type, a floating gate electrode, an interlayer film and a control gate electrode successively formed;
source and drain regions of a second conductivity type formed in the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween;
a first semiconductor region which is adjacent to the drain region and formed by introducing an impurity of the second conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively lower than that of the drain region; and
a second semiconductor region which is adjacent to the first semiconductor region and formed by introducing an impurity of the first conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively higher than that of the channel region, wherein the control gate electrode is electrically connected to its corresponding word line, and a negative voltage is applied to each non-selected word line upon a write operation.
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Abstract
A parallel connection-type nonvolatile memory semiconductor device comprises a plurality of memory cells disposed on a semiconductor substrate in matrix form, each including a gate insulating film, a floating gate electrode, an interlayer film and a control gate electrode successively formed so as to cover a channel region on a main surface of the semiconductor substrate, of a first conductivity type; a second conductivity type source and drain regions formed on the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween; a first semiconductor region which is adjacent to the drain region and formed by introducing a second conductivity type impurity in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which is substantially lower than the drain region in impurity concentration; and a punch-through stopper layer which is adjacent to the first semiconductor region and formed by introducing a first conductivity type impurity in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which is substantially higher than the channel region in impurity concentration, and wherein the source regions and drain regions of the plurality of nonvolatile memory cells are parallel-connected to one another in respective columns, word lines some of which constitute the control gate electrodes of the plurality of nonvolatile memory cells, extend in respective rows, a voltage is applied to at least one word line, which is set so as to serve as a selected word line, and when carriers are stored in a floating gate electrode of each selected memory cell, a negative voltage is applied to other non-selected word lines other than the selected word line.
17 Citations
20 Claims
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1. A semiconductor device comprising:
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a plurality of nonvolatile memory cells arranged on a semiconductor substrate in matrix form, each including, a gate insulating film covering a channel region in a main surface of the semiconductor substrate of a first conductivity type, a floating gate electrode, an interlayer film and a control gate electrode successively formed;
source and drain regions of a second conductivity type formed in the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween;
a first semiconductor region which is adjacent to the drain region and formed by introducing an impurity of the second conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively lower than that of the drain region; and
a second semiconductor region which is adjacent to the first semiconductor region and formed by introducing an impurity of the first conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively higher than that of the channel region, wherein the control gate electrode is electrically connected to its corresponding word line, and a negative voltage is applied to each non-selected word line upon a write operation.
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2. A semiconductor device comprising:
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a plurality of nonvolatile memory cells arranged on a semiconductor substrate in matrix form, each including, a gate insulating film covering a channel region in a main surface of the semiconductor substrate of a first conductivity type, a floating gate electrode, an interlayer film and a control gate electrode successively formed;
source and drain regions of a second conductivity type formed in the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween;
a first semiconductor region which is adjacent to the drain region and formed by introducing an impurity of a second conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively lower than that of the drain region; and
a second semiconductor region which is adjacent to the first semiconductor region and formed by introducing an impurity of the first conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively higher than that of the channel region, wherein the source and drain regions of the plurality of nonvolatile memory cells are parallel-connected to one another in respective columns, wherein word lines which constitute the control gate electrodes of the plurality of nonvolatile memory cells, extend in respective rows, wherein a voltage is applied to at least one word line, which is set so as to serve as a selected word line, and wherein when carriers are stored in a floating gate electrode of a nonvolatile memory cell connected to the selected word line, a negative voltage is applied to other non-selected word lines other than the selected word line. - View Dependent Claims (3, 4, 5, 6, 7)
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8. A method of manufacturing a semiconductor device having a plurality of nonvolatile memory cells arranged on a semiconductor substrate in matrix form, and wherein source and drain regions of the plurality of nonvolatile memory cells are parallel-connected to one another in respective columns and word lines which constitute control gate electrodes of the plurality of nonvolatile memory cells, extend in respective rows, the method comprising the steps of:
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(a) forming a gate insulating film covering a channel region in a main surface of the semiconductor substrate of a first conductivity type, a floating gate electrode, an interlayer film and a control gate electrode;
(b) forming the source and drain regions of a second conductivity type on the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween;
(c) introducing an impurity of a first conductivity type into the semiconductor substrate from an end on the drain side, of the floating gate electrode to thereby form a second semiconductor region adjacent to the drain region and having an impurity concentration relatively higher than that of the channel region; and
(d) introducing an impurity of a second conductivity type into the semiconductor substrate from an end on the drain side, of the floating gate electrode to thereby form a first semiconductor region adjacent to the drain region and having an impurity concentration relatively lower than that of the drain region. - View Dependent Claims (12, 14, 16, 17, 19, 20)
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9. A method of manufacturing a semiconductor device having a plurality of nonvolatile memory cells arranged on a semiconductor substrate in matrix form, and wherein source regions and drain regions of the plurality of nonvolatile memory cells are parallel-connected to one another in respective columns and word lines which constitute control gate electrodes of the plurality of nonvolatile memory cells, extend in respective rows, the method comprising the steps of:
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(a) forming a gate insulating film covering a channel region in a main surface of the semiconductor substrate of a first conductivity type, a floating gate electrode, an interlayer film and a control gate electrode;
(b) forming the source and drain regions of a second conductivity type on the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween;
(c) introducing an impurity of the first conductivity type into the semiconductor substrate from both ends of the floating gate electrode to thereby form a second semiconductor region adjacent to the drain region and having an impurity concentration relatively higher than that of the channel region and a third semiconductor region adjacent to the source region and having an impurity concentration relatively higher than that of the channel region; and
(d) introducing an impurity of a second conductivity type into the semiconductor substrate from an end on the drain side, of the floating gate electrode to thereby form a first semiconductor region adjacent to the drain region and having an impurity concentration relatively lower than that of the drain region.
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10. A method of manufacturing a semiconductor device having a plurality of nonvolatile memory cells arranged on a semiconductor substrate in matrix form, and wherein source regions and drain regions of the plurality of nonvolatile memory cells are parallel-connected to one another in respective columns and word lines which constitute control gate electrodes of the plurality of nonvolatile memory cells, extend in respective rows, the method comprising the steps of:
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(a) forming a gate insulating film covering a channel region in a main surface of the semiconductor substrate of a first conductivity type, a floating gate electrode, an interlayer film and a control gate electrode;
(b) introducing an impurity of a second conductivity type into the semiconductor substrate from one end of the floating gate electrode to thereby form the drain region, further introducing an impurity of the second conductivity type therein to thereby form a first semiconductor region adjacent to the drain region and having an impurity concentration relatively lower than that of the drain region, and furthermore introducing an impurity of the first conductivity type therein to thereby form a second semiconductor region adjacent to the first semiconductor region and having an impurity concentration relatively higher than that of the channel region; and
(c) introducing an impurity of the second conductivity type into the semiconductor substrate from the other end of the floating gate electrode to thereby form the source region. - View Dependent Claims (15, 18)
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11. A method of manufacturing a semiconductor device having a plurality of nonvolatile memory cells arranged on a semiconductor substrate in matrix form, and wherein source regions and drain regions of the plurality of nonvolatile memory cells are parallel-connected to one another in respective columns and word lines which constitute control gate electrodes of the plurality of nonvolatile memory cells, extend in respective rows, the method comprising the steps of:
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(a) forming a gate insulating film covering a channel region in a main surface of the semiconductor substrate of a first conductivity type, a floating gate electrode, an interlayer film and a control gate electrode;
(b) introducing an impurity of a second conductivity type into the semiconductor substrate from one end of the floating gate electrode to thereby form the drain region, further introducing an impurity of the second conductivity type therein to thereby form a first semiconductor region adjacent to the drain region and having an impurity concentration relatively lower than that of the drain region, and furthermore introducing an impurity of a first conductivity type therein to thereby form a second semiconductor region adjacent to the first semiconductor region and having an impurity concentration relatively higher than that of the channel region;
(c) introducing an impurity of the second conductivity type into the semiconductor substrate from the other end of the floating gate electrode to thereby form the source region, and further introducing an impurity of the first conductivity type therein to thereby form a third semiconductor region adjacent to the source region and having an impurity concentration relatively higher than that of the channel region. - View Dependent Claims (13)
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Specification