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Self-aligned power MOSFET with enhanced base region

  • US 20020074585A1
  • Filed: 02/22/2002
  • Published: 06/20/2002
  • Est. Priority Date: 05/17/1988
  • Status: Abandoned Application
First Claim
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1. A vertical double-diffused insulated gate transistor, comprising:

  • a substrate comprising silicon with doping of a first dopant type;

    a gate oxide layer disposed over the surface of the substrate;

    a gate conductive layer on the gate oxide layer, the gate oxide layer and the gate conductive layer collectively defining an opening of a defined outline characteristic;

    double-diffused dopant means of opposite second and first dopant types disposed within the substrate to define first and second PN junctions spaced laterally apart under the gate oxide layer and contoured in accordance with the defined outline characteristic, the PN junctions arranged to define portions of a field effect transistor, the portions including a source region of the first dopant type in the substrate subjacent the defined outline characteristic and bounded by the first PN junction, a drain region of the first dopant type bounded by the second PN junction and spaced laterally from the defined outline characteristic and extending downwardly into the substrate, and a body region of the second dopant type extending between the first and second PN junctions with a channel portion thereof underlying the gate oxide layer and the gate conductive layer, the channel portion operable under field effect to conduct current between the source and drain regions; and

    a source conductive layer on the upper surface of the substrate and contacting the source region within the opening, the source conductive layer spaced apart and electrically separate from the gate conductive layer;

    the gate conductive layer comprising doped polysilicon on the gate oxide layer and a metal layer coextending over the doped polysilicon.

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