Self-aligned power MOSFET with enhanced base region
First Claim
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1. A vertical double-diffused insulated gate transistor, comprising:
- a substrate comprising silicon with doping of a first dopant type;
a gate oxide layer disposed over the surface of the substrate;
a gate conductive layer on the gate oxide layer, the gate oxide layer and the gate conductive layer collectively defining an opening of a defined outline characteristic;
double-diffused dopant means of opposite second and first dopant types disposed within the substrate to define first and second PN junctions spaced laterally apart under the gate oxide layer and contoured in accordance with the defined outline characteristic, the PN junctions arranged to define portions of a field effect transistor, the portions including a source region of the first dopant type in the substrate subjacent the defined outline characteristic and bounded by the first PN junction, a drain region of the first dopant type bounded by the second PN junction and spaced laterally from the defined outline characteristic and extending downwardly into the substrate, and a body region of the second dopant type extending between the first and second PN junctions with a channel portion thereof underlying the gate oxide layer and the gate conductive layer, the channel portion operable under field effect to conduct current between the source and drain regions; and
a source conductive layer on the upper surface of the substrate and contacting the source region within the opening, the source conductive layer spaced apart and electrically separate from the gate conductive layer;
the gate conductive layer comprising doped polysilicon on the gate oxide layer and a metal layer coextending over the doped polysilicon.
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Abstract
A power MOSFET transistor is formed on a substrate including a source, body layer, and drain layer and an optional fourth layer for an IGBT. The device is characterized by a conductive gate having a high conductivity metal layer coextensive with a polysilicon layer for high power and high speed operation.
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Citations
40 Claims
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1. A vertical double-diffused insulated gate transistor, comprising:
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a substrate comprising silicon with doping of a first dopant type;
a gate oxide layer disposed over the surface of the substrate;
a gate conductive layer on the gate oxide layer, the gate oxide layer and the gate conductive layer collectively defining an opening of a defined outline characteristic;
double-diffused dopant means of opposite second and first dopant types disposed within the substrate to define first and second PN junctions spaced laterally apart under the gate oxide layer and contoured in accordance with the defined outline characteristic, the PN junctions arranged to define portions of a field effect transistor, the portions including a source region of the first dopant type in the substrate subjacent the defined outline characteristic and bounded by the first PN junction, a drain region of the first dopant type bounded by the second PN junction and spaced laterally from the defined outline characteristic and extending downwardly into the substrate, and a body region of the second dopant type extending between the first and second PN junctions with a channel portion thereof underlying the gate oxide layer and the gate conductive layer, the channel portion operable under field effect to conduct current between the source and drain regions; and
a source conductive layer on the upper surface of the substrate and contacting the source region within the opening, the source conductive layer spaced apart and electrically separate from the gate conductive layer;
the gate conductive layer comprising doped polysilicon on the gate oxide layer and a metal layer coextending over the doped polysilicon. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. A power MOSFET comprising:
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a substrate, the substrate comprising drain semiconductor material comprising a first dopant type;
source semiconductor material comprising a dopant type the same as the first dopant type;
channel semiconductor material comprising a second dopant type disposed between the source semiconductor material and the drain semiconductor material, the channel semiconductor material to operate under field effect to conduct current between the source semiconductor material and the drain semiconductor material;
a conductive gate structure to apply an electric field to the channel semiconductor material;
an oxide layer disposed between the conductive gate structure and the channel semiconductor material;
the conductive gate structure comprising doped polysilicon contacting the oxide layer and metal disposed substantially coextensively over the doped polysilicon;
dielectric material disposed over the substrate; and
metallization over the dielectric material, the metallization contacting the gate structure through openings in the dielectric material. - View Dependent Claims (33, 34, 35, 36, 38, 39, 40)
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37. An insulated gate power transistor, comprising:
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a substrate comprising silicon having a first dopant type, the substrate defining a surface;
a gate oxide layer disposed over the surface;
a gate conductive layer on the gate oxide layer, the gate oxide layer and the gate conductive layer comprising walls defining an outline for an opening;
double-diffused dopant region disposed within the substrate, the double-diffused dopant region comprising;
first and second dopant type regions defining respective first and second boundary contours within the substrate, the boundary contours meeting the surface of the substrate under the gate oxide layer at separate relative placements defined in relationship to the opening;
the first dopant type region in the substrate comprising a source region to a field effect transistor proximate the defined outline and extending to the first boundary;
the second dopant type region comprising a body region to the field effect transistor between the first and the second boundaries and comprising a channel portion in contact with the gate oxide layer to received field effect of the gate conductive layer; and
the substrate laterally spaced from the first and second boundaries and away from the defined outline for the opening comprising a drain region to the field effect transistor, the drain region comprising first dopant type and extending downwardly into the substrate; and
a source conductor over the substrate and contacting the source region through the opening, the source conductor separate from the gate layer;
the gate conductive layer comprising a polysilicon layer on the gate oxide layer and a layer of aluminum covering the polysilicon layer.
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Specification