Self-aligned power MOSFET with enhanced base region

• US 20020074585A1
• Filed: 02/22/2002
• Published: 06/20/2002
• Est. Priority Date: 05/17/1988
• Status: Abandoned Application

• Current Assignee: Microsemi Corp. - Advanced Technology Center (Microchip Technology Incorporated)
• Original Assignee: Microsemi Corp. - Advanced Technology Center (Microchip Technology Incorporated)
• Inventors: Meyer, Theodore O., Pike, Douglas A. Jr., Mosier, John W. II, Tsang, Dah Wen
• Application Number:
  US10/080,871
• Publication Number:
  US 20020074585A1
• Time in Patent Office: Days
• US Class Current: 257/302
• CPC Class Codes: H01L 21/221 of killers
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOSFET transistor is formed on a substrate including a source, body layer, and drain layer and an optional fourth layer for an IGBT. The device is characterized by a conductive gate having a high conductivity metal layer coextensive with a polysilicon layer for high power and high speed operation.

Claims

1. A vertical double-diffused insulated gate transistor, comprising:

a substrate comprising silicon with doping of a first dopant type;

a gate oxide layer disposed over the surface of the substrate;

a gate conductive layer on the gate oxide layer, the gate oxide layer and the gate conductive layer collectively defining an opening of a defined outline characteristic;

double-diffused dopant means of opposite second and first dopant types disposed within the substrate to define first and second PN junctions spaced laterally apart under the gate oxide layer and contoured in accordance with the defined outline characteristic, the PN junctions arranged to define portions of a field effect transistor, the portions including a source region of the first dopant type in the substrate subjacent the defined outline characteristic and bounded by the first PN junction, a drain region of the first dopant type bounded by the second PN junction and spaced laterally from the defined outline characteristic and extending downwardly into the substrate, and a body region of the second dopant type extending between the first and second PN junctions with a channel portion thereof underlying the gate oxide layer and the gate conductive layer, the channel portion operable under field effect to conduct current between the source and drain regions; and

a source conductive layer on the upper surface of the substrate and contacting the source region within the opening, the source conductive layer spaced apart and electrically separate from the gate conductive layer;

the gate conductive layer comprising doped polysilicon on the gate oxide layer and a metal layer coextending over the doped polysilicon.

2. A device according to claim 1, wherein the region of the second dopant type of the dopant means comprises a first portion and a second portion, the first portion disposed alongside the source region and having a first doping concentration, the second portion contained within the first portion and extending laterally beneath the source conductive material, the second portion having a second doping concentration greater than the first doping concentration.

3. A device according to claim 1, further comprising insulative sidewall spacers disposed along the defined outline characteristic, the sidewall spacers laterally separating the gate conductive layer and the source conductive layer.

4. A device according to claim 1, further comprising a low-resistivity contact layer between the source region and the source conductive layer.

5. A device according to claim 3 wherein the metal layer of the gate conductive layer is aligned with the doped polysilicon between the sidewall spacers.

6. A device according to claim 1 wherein the source conductive layer comprises aluminum.

7. A device according to claim 1, wherein the metal layer of the gate conductive layer comprises aluminum.

8. A device according to claim 7, wherein the source conductive layer comprises aluminum.

9. A device according to claim 7, further comprising:

a dielectric layer disposed over the gate conductive layer; and

metallization disposed over the dielectric layer and contacting the gate conductive layer through openings in the dielectric layer.

10. A device according to claim 9, wherein the dielectric layer comprises at least one of the group consisting of oxide, nitride, oxy-nitride, glass and phosphosilicate glass (PSG).

11. A device according to claim 9, wherein the dielectric layer comprises first and second layers of dielectric material, the dielectric material of the second layer different from the dielectric material of the first layer.

12. A device according to claim 7 further comprising:

a dielectric layer disposed over the gate conductive layer; and

metallization disposed over the dielectric layer and the gate conductive layer, the metallization contacting the source conductive layer through openings in the dielectric layer.

13. A device according to claim 12, wherein the dielectric layer comprises at least one of the group consisting of oxide, nitride, oxy-nitride, glass and phosphosilicate glass (PSG).

14. A device according to claim 12, wherein the dielectric layer comprises first and second layers of dielectric material, the dielectric material of the second layer different from the dielectric material of the first layer.

15. A device according to claim 1, wherein the metal layer of the gate conductive layer comprises a plateable metal.

16. A device according to claim 15, wherein the plateable metal comprises aluminum.

17. A device according to claim 1, wherein the metal layer of the gate conductive layer comprises refractory metal coextending over the doped polysilicon and plateable metal coextending over the refractory metal.

18. A device according to claim 1, wherein the metal layer of the gate conductive layer comprises refractory metal coextending over the doped polysilicon and aluminum coextending over the refractory metal.

19. A device according to claim 1, wherein the gate conductive layer comprises refractory metal silicide over the doped polysilicon and the metal layer comprises a plateable metal.

20. A device according to claim 19, wherein the plateable metal comprises aluminum.

21. A device according to claim 1, wherein the metal layer of the gate conductive layer comprises first and second layers of metal.

22. A device according to claim 1, wherein a portion of the substrate surface defines a trench, the source region of the double-diffused dopant means meeting a region of the substrate surface at the periphery of the trench.

23. A device according to claim 22, further comprising insulative sidewall spacers disposed along the defined outline characteristic, the source conductive layer being confined between walls of the trench and the sidewall spacers and the gate conductive layer outside the sidewall spacers.

24. A device according to claim 23, further comprising a low-resistivity contact layer disposed between the source region and the source conductive layer.

25. A device according to claim 24, wherein the low-resistivity contact layer comprises a shallow diffusion of the same dopant type as the source region.

26. A device according to claim 25, in which the low-resistivity contact layer comprises at least one of a layer of refractory metal and a refractory metal silicide.

27. A device according to claim 1, further comprising:

an insulating layer disposed over the gate conductive layer; and

metal disposed over the insulating layer and contacting the gate conductive layer through openings in the insulating layer.

28. A device according to claim 27, wherein the insulating layer comprises at least one of the group consisting of oxide, nitride, oxy-nitride, glass and phosphosilicate glass (PSG).

29. A device according to claim 28, wherein the insulating layer comprises first and second layers of dielectric material, the dielectric material of the second layer different from the dielectric material of the first layer.

30. A device according to claim 1, further comprising:

an insulating layer disposed over the gate conductive layer; and

metal disposed over the insulating layer and contacting the source conductive layer through openings in the insulating layer.

31. A device according to claim 30, wherein the insulating material comprises at least one of the group consisting of oxide, nitride, oxy-nitride, glass and phosphosilicate glass (PSG).

32. A power MOSFET comprising:

a substrate, the substrate comprising drain semiconductor material comprising a first dopant type;

source semiconductor material comprising a dopant type the same as the first dopant type;

channel semiconductor material comprising a second dopant type disposed between the source semiconductor material and the drain semiconductor material, the channel semiconductor material to operate under field effect to conduct current between the source semiconductor material and the drain semiconductor material;

a conductive gate structure to apply an electric field to the channel semiconductor material;

an oxide layer disposed between the conductive gate structure and the channel semiconductor material;

the conductive gate structure comprising doped polysilicon contacting the oxide layer and metal disposed substantially coextensively over the doped polysilicon;

dielectric material disposed over the substrate; and

metallization over the dielectric material, the metallization contacting the gate structure through openings in the dielectric material.

33. A power MOSFET according to claim 32 wherein the source semiconductor material, channel semiconductor material, and drain semiconductor material are configured to define a laterally-oriented channel structure underneath the gate oxide layer to receive field effect of the gate structure, the lateral orientation substantially parallel to an upper surface of the substrate.

34. A power MOSFET according to claim 33, wherein the conductive gate structure defines a finger;

the power MOSFET comprising a plurality of such fingers disposed over the substrate, the plurality of fingers laterally separated to define a striped pattern over the substrate.

35. A device according to claim 32, further comprising a source conductive layer over the substrate and selectively contacting the source semiconductor material;

the source conductive layer comprising a layer of metal.

36. A device according to claim 35, in which a portion of the metallization over the dielectric material and the gate conductive layer contacts the source conductive layer through openings in the dielectric material.

38. A device according to claim 37 in which the source conductor comprises aluminum.

39. A device according to claim 37, further comprising:

an insulating layer disposed over the substrate and the gate conductive layer; and

an aluminum layer disposed over the insulating layer and contacting the gate conductive layer through openings in the insulating layer.

40. A device according to claim 37, further comprising:

an insulating layer disposed over the substrate and the gate conductive layer; and

an aluminum layer disposed over the insulating layer and contacting the gate conductive layer, the aluminum layer contacting the source conductor through openings in the insulating layer.

37. An insulated gate power transistor, comprising:

a substrate comprising silicon having a first dopant type, the substrate defining a surface;

a gate oxide layer disposed over the surface;

a gate conductive layer on the gate oxide layer, the gate oxide layer and the gate conductive layer comprising walls defining an outline for an opening;

double-diffused dopant region disposed within the substrate, the double-diffused dopant region comprising;

first and second dopant type regions defining respective first and second boundary contours within the substrate, the boundary contours meeting the surface of the substrate under the gate oxide layer at separate relative placements defined in relationship to the opening;

the first dopant type region in the substrate comprising a source region to a field effect transistor proximate the defined outline and extending to the first boundary;

the second dopant type region comprising a body region to the field effect transistor between the first and the second boundaries and comprising a channel portion in contact with the gate oxide layer to received field effect of the gate conductive layer; and

the substrate laterally spaced from the first and second boundaries and away from the defined outline for the opening comprising a drain region to the field effect transistor, the drain region comprising first dopant type and extending downwardly into the substrate; and

a source conductor over the substrate and contacting the source region through the opening, the source conductor separate from the gate layer;

the gate conductive layer comprising a polysilicon layer on the gate oxide layer and a layer of aluminum covering the polysilicon layer.