Multi-chip integrated circuit module

• US 20020074668A1
• Filed: 12/14/2000
• Published: 06/20/2002
• Est. Priority Date: 12/14/2000
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Sprogis, Edmund Juris, Hofstee, Harm Peter, Montoye, Robert Kevin
• Granted Patent: US 6,507,115 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A multi-chip module is disclosed in which a first die connects to a second set of die via a set of C4 connections within a single package. Low resistivity signal posts are provided within the lateral separation between adjacent die in the second set of die. These signal posts are connectable to externally supplied power signals. The power signals provided to the signals posts are routed to circuits within the second set of die over relatively short metallization interconnects. The signal posts may be connected to thermally conductive via elements and the package may include heat spreaders on upper and lower package surfaces. The first die may comprise a DRAM while the second set of die comprise portions of a general purpose microprocessor. The power signals provided to the second set of die may be connected to a capacitor terminal in the first die to provide power signal decoupling.

Claims

1. A multi-chip module comprising:

a first semiconductor die having an active surface;

a second set of semiconductor die, wherein active surfaces of each of the second set of devices are oriented to face the active surface of the first device; and

signal posts located between adjacent pairs of the second set of semiconductor die, wherein the signals posts are connectable at a first end to an external power supply signal and wherein the signal posts are connectable at a second end directly to contacts situated on the active surface of the first semiconductor die and connectable through the first semiconductor die to the second semiconductor die.

2. The method of claim 1, wherein the first die comprises a memory device and the second set of die collectively comprise a processor device.

3. The method of claim 1, further comprising a perimeter of ball grid array structures surrounding a heat spreader attached to a package enclosing the first die and the second set of die.

4. The method of claim 3, further comprising a heat spreader attached to an upper surface of the package.

5. The method of claim 1, wherein any adjacent pair of the signal posts include a first signal post connectable to ground and a second signal post connectable to a VDD power supply signal.

6. The method of claim 1, wherein the signal posts are connected to thermally conductive elements of the package including a thermal via.

7. The method of claim 1, wherein at least one of the signal posts is connected to a capacitive structure in the first die.

8. An assembly comprising:

a printed circuit board, wherein the circuit board defines an aperture;

a multi-chip module attached to the circuit board positioned above the aperture in the circuit board, wherein the module includes a first semiconductor die enclosed within a package, a second set of semiconductor die enclosed with the package, wherein an active surface of each of the second set of die is in close proximity to an active surface of the first die, and signal posts located between adjacent pairs of the second set of die, wherein the signals posts are connectable at a first end to an external power supply signal and wherein the signal posts are connectable at a second end directly to contacts situated on the active surface of the first semiconductor die and connectable through the first semiconductor die to the second semiconductor die;

a first heat sink located above the circuit board in close proximity to an upper surface of the module; and

a second heat sink in close proximity to a lower surface of the module and extending through the circuit board aperture.

9. The assembly of claim 8, wherein the first die comprises a memory device and the second set of die collectively comprise a processor device.

10. The assembly of claim 8, wherein a bottom surface of the module includes a perimeter of ball grid array structures surrounding a heat spreader.

11. The assembly of claim 10, further comprising a heat spreader attached to an upper surface of the module.

12. The assembly of claim 8, wherein any adjacent pair of the signal posts include a first signal post connectable to ground and a second signal post connectable to a VDD power supply signal.

13. The assembly of claim 8, wherein the signal posts are connected to thermal via elements of the module.

14. The assembly of claim 8, wherein at least one of the signal posts is connected to a capacitive structure in the first die.

16. The system of claim 15, wherein the memory die comprises a dynamic memory.

17. The system of claim 16, wherein the memory die includes a decoupling capacitor structure and wherein the signal posts are connected to a terminal of the capacitor.

18. The system of claim 15, wherein a signal post is connected to a power signal interconnect in the memory device and further wherein the power signal interconnect is connected to one of the processor die via a C4 connection.

19. The system of claim 15, wherein a bottom surface of a module enclosing the memory die and the set of processor die includes a perimeter of ball grid array structures surrounding a heat spreader.

20. The system of claim 19, further comprising a heat spreader attached to an upper surface of the module.

21. The system of claim 15, wherein any adjacent pair of the signal posts include a first signal post connectable to ground and a second signal post connectable to a VDD power supply signal.

22. The system of claim 15, wherein the signal posts are connected to thermal via elements of the module.

15. A data processing system comprising:

a memory die having an active surface;

a set of processor die each having an active surface arranged in close proximity to the active surface of the memory die, wherein each of the processor die is connected to the memory device via a plurality of controlled collapse chip connections; and

a set of signal posts positioned between adjacent pairs of the processor die, wherein the signal posts are connectable at a first end to an external power supply and further wherein the signal posts are connectable at a second end to contacts situated on the active surace of the first die and connectable through the memory die to the corresponding adjacent pair of processor die.