Apparatus and method for evaluating semiconductor structures and devices

• US 20020075017A1
• Filed: 12/14/2000
• Published: 06/20/2002
• Est. Priority Date: 01/04/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Wilk, Glen D., Edwards, Henry L., Moise, Theodore S.
• Granted Patent: US 6,498,502 B2
• Time in Patent Office: Days
• US Class Current: 324/750
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: G01R 31/312 by capacitive methods
• CPC Class Codes: Y10S 977/852 for detection of specific nanostructure sample or nanostructure-related property

Abstract

An apparatus and method for evaluating semiconductor structures and devices are provided. The present invention provides a method for evaluating at least one selected electrical property of a semiconductor device (201) in relation to a selected geometric dimension of the semiconductor device (201). The method further includes forming a plurality of semiconductor devices (201) on a substrate (202), the devices (201) having at least one geometric dimension, measuring the at least one electrical property of at least one of the semiconductor devices (201) using a scanning probe microscopy based technique, and determining a relationship between the measured electrical property and the selected geometric dimension of the semiconductor device (201). The method further includes evaluating at least one semiconductor fabrication process based upon the determined relationship.

Claims

1. A method for evaluating at least one selected electrical property of a semiconductor device in relation to a selected geometric dimension of the semiconductor device comprising:

forming a plurality of semiconductor devices on a substrate, the devices having at least one geometric dimension;

measuring the at least one electrical property of at least one of the semiconductor devices using a scanning probe microscopy based technique;

determining a relationship between the measured electrical property and the selected geometric dimension of the semiconductor device; and

evaluating at least one semiconductor fabrication process based upon the determined relationship.

2. The method of claim 1, further comprising measuring a topography of the semiconductor device using a scanning probe microscopy based technique.

3. The method of claim 2, wherein the measuring the topography comprises measuring the topography in a region proximal to the measured electrical property.

4. The method of claim 1, wherein the measuring the at least one electrical property includes measuring the property using a nanoscopic conductive probe.

5. The method of claim 1, wherein at least one of the devices includes at least one electrode.

6. The method of claim 1, further comprising measuring at least one of the semiconductor devices using a scanning capacitance microscope.

7. The method of claim 1, wherein the selected geometric dimension includes a geometric dimension of less than one micrometer.

8. The method of claim 1, wherein the measuring the at least one electrical property comprises simultaneously measuring the selected geometric dimension of the semiconductor device.

9. A method for evaluating a semiconductor device, the method comprising:

providing the semiconductor device;

measuring a first characteristic of the device using a first scanning probe microscopy technique;

measuring an electrical property of the device using second scanning probe microscopy technique;

determining variations in the semiconductor device based upon the measured first characteristic and the measured electrical property; and

wherein the first characteristic and the electrical property are measured in a proximal region to one another.

10. The method of claim 9, wherein the providing includes forming an array of semiconductor devices, at least one of the devices having a submicron geometric element.

11. The method of claim 9, wherein the first characteristic and the electrical property are measured simultaneously.

12. The method of claim 9, wherein the proximal region includes the same location.

13. The method of claim 9, wherein the determining variations includes establishing a relationship between the measured first characteristic and the measured electrical property.

14. The method of claim 9, wherein the evaluating includes evaluating an oxide integrity of the device.

15. The method of claim 9, wherein the determining includes correlating a geometric dimension variation of the device to a semiconductor process variation.

16. The method of claim 9, wherein the first characteristic includes measuring a topography of the semiconductor device.

18. The system of claim 17, wherein the program further includes at least one instruction configured to evaluate at least one semiconductor fabrication process based upon the determined relationship.

19. The system of claim 17, wherein the probe further comprises a conductive element.

20. The system of claim 17, wherein the probe is configured as nanoscopic probe.

17. A system for evaluating semiconductor devices comprising:

a processor;

a storage medium operably coupled to the processor;

a scanning probe microscopy device, operably coupled to the processor to evaluate semiconductor devices;

wherein the scanning probe microscopy includes a probe configured to measure at least one electrical property of the semiconductor device; and

wherein the processor includes a program of instructions for evaluating a semiconductor device, the program of instructions including at least one instruction configured to measure the at least one electrical property and determining a relationship between the measured electrical property and at least one geometric dimension of the device.