Low component circuit for reducing power dissipation capacitance

• US 20020075044A1
• Filed: 12/04/2001
• Published: 06/20/2002
• Est. Priority Date: 12/19/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hinterscher, Eugene B.
• Granted Patent: US 6,509,764 B2
• Time in Patent Office: Days
• US Class Current: 327/108
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/01707 in asynchronous circuits

Abstract

An improved pre-driver circuit 33, which uses only three additional components to bypass the back-gate current blocking diodes for increased circuit speed during normal operation, while reducing the I_off current and satisfying over-voltage tolerant specification. This unique circuit uses the pre-driver'"'"'s tri-state input signal to control the pull-up path of the pre-driver circuit'"'"'s upper output (UOP) transistor 3010.

Claims

1. A pre-driver/driver circuit to prevent an increase in dynamic operating current and power dissipation capacitance in said circuit, comprising:

an upper pre-driver/driver stage and a lower pre-driver/driver stage, the output of said upper and lower stages being combined and coupled to an input/output pin and the input of said stages being tied together and coupled to an In signal;

said upper pre-driver stage having a control input coupled to a {overscore (Tri-state)} control signal and said lower pre-driver state having a control input coupled to a Tri-state control signal;

a Schottky and a pn blocking diode wired in parallel and inserted between a V_dd power supply and said upper pre-driver/driver stage'"'"'s back-gate and control circuitry for blocking current flow when said pre-driver stages are in the Tri-state mode; and

a back-gate current blocking diode by-pass circuit for by-passing the voltage drop across said blocking diodes to assure that the upper output transistor in said upper pre-driver/driver stage turns OFF during normal operation of said pre-driver circuit.

2. The pre-driver/driver circuit of claim 1, wherein said blocking diode by-pass circuit further comprises:

a n-channel control transistor, the source being coupled to gnd, the gate coupled to said {overscore (Tri-state)} signal, and the drain coupled to the gate of a first p-channel transistor and to the source of a second p-channel transistor;

the source of said first p-channel transistor coupled to the gate of said second p-channel transistor and to a power source;

the drain of said first p-channel transistor coupled to a first output of said by-pass circuit and the drain of said second p-channel circuit coupled to a second output of said by-pass circuit and to said pre-driver/driver input/output pin.

3. The pre-driver/driver circuit of claim 1, wherein:

said upper pre-driver/driver stage consists of an input control circuit and an output driver circuit; and

said lower pre-driver/driver stage consists of an input control circuit and an output driver circuit.

4. The pre-driver/driver circuit of claim 3, wherein said input control circuit of said upper pre-driver/driver stage, used to control the gate of said upper output device, further comprises:

first and second n-channel transistors connected in series with the source of said first transistor connected to the drain of said second transistor, the gate of said first transistor being coupled to said In signal, the gate of said second transistor being couple to said {overscore (Tri-state)} signal, and the source of said second transistor coupled to gnd; and

the source of a first p-channel transistor being coupled to said first output of said pre-driver pull-up circuit, the source of said second transistor being coupled to the negative side of said blocking diodes, and the drains of said first and second p-channel transistors connected together and coupled to the drain of said first n-channel transistor and to the control output of said upper output driver circuit, and the gate of said first p-channel transistor coupled to said In signal and the gate of said second p-channel transistor coupled to said {overscore (Tri-state)} signal and the back-gate of first and second p-channel transistors coupled to the negative side of said blocking diodes.

5. The pre-driver/driver circuit of claim 3, wherein said output driver circuit of said upper pre-driver/driver stage further comprises:

an upper output p-channel transistor, the gate being coupled to said output of said upper pre-driver stage output, the source coupled to a V_dd source, and the drain coupled to said input/output pin;

second and third p-channel transistors for clamping the voltage at said output pin to the gate of said upper output transistor, thereby turning OFF said output transistor, the gates of said second and third transistors being coupled to said V_dd source;

the drains of said second and third transistor coupled to said output pin, the source of said second transistor coupled to the output of said upper pre-driver stage input control circuit and to the gate of said upper output transistor, and the source of said third transistor coupled to the negative side of said blocking diodes.

6. The pre-driver/driver circuit of claim 3, wherein said input control circuit of said lower pre-driver/driver stage, further comprises:

first and second p-channel transistor connected in series with the drain of said first transistor connected to the source of said second transistor, the gate of said first transistor being coupled to said Tri-state input signal and the gate of said second transistor being coupled to said input signal, and the source of said first transistor connected to a said V_dd source; and

first and second n-channel transistors connected in parallel with sources of said transistors coupled to gnd, and drains of said first and second transistors connected together and coupled to the drain of said second p-channel transistor and to the control output of said lower pre-driver input control circuit, the gate of said second transistor coupled to said In signal, and the gate of said first transistor coupled to said Tri-state input signal.

7. The pre-driver/driver circuit of claim 3, wherein said output driver circuit of said lower pre-driver state, used to properly supply and sink current to and from said input/output pin, further comprises:

a n-channel transistor with gate coupled to the said output of said lower pre-driver input control circuit, the source connected to gnd, and the drain of said transistor being coupled to the first side of a ballast resistor, and the second side of said ballast resistor being coupled to said input/output pin.

8. The pre-driver/driver circuit of claim 3, wherein during normal operation of said pre-driver in high frequency switching conditions, the gate of said upper output transistor is pulled up to said V_dd rail, completely turning OFF said upper output transistor, thereby preventing an increase in said circuit'"'"'s dynamic operating current and power dissipation capacitance.

9. The pre-driver/driver circuit of claim 3, wherein said blocking diode by-pass circuitry requires only 3 components, thereby reducing the power consumption and chip area requirements of the pre-driver integrated circuit.

10. The pre-driver/driver circuit of claim 3, wherein during I_off condition where said V_dd equals zero volts, said by-pass circuit'"'"'s said second p-channel transistor is in and ON state ready to clamp the gate of said by-pass circuit'"'"'s said first p-channel transistor, said upper pre-driver/driver stage'"'"'s said second and third p-channel transistors are in an ON condition, ready to clamp said input/output pin voltage to the gate of said upper output transistor, so that when said input/output pin voltage is ramped up to a given high voltage, said by-pass circuit'"'"'s first p-channel transistor will turn OFF through said by-pass circuit'"'"'s second p-channel transistor and said upper output transistor will turn OFF through said upper pre-driver stage'"'"'s second and third p-channel clamping transistors.

11. The pre-driver/driver circuit of claim 3, wherein during an over-voltage condition with said Tri-state signal being in the ON state and both said n-channel transistor of said by-pass circuitry is in the OFF state and said second p-channel transistor in said upper pre-driver control circuit is in the ON state, and when said input/output pin is ramped to a voltage v_t above said V_dd, said second p-channel clamping transistors in said by-pass circuitry stage and said second and third p-channel clamping transistors of said upper output stage turn ON, thereby clamping said input/output pin voltage to the gates of said by-pass circuit'"'"'s p-channel transistor and said pre-driver'"'"'s upper output transistor, respectively.