VCO gain self-calibration for low voltage phase lock-loop applications

• US 20020075080A1
• Filed: 12/13/2000
• Published: 06/20/2002
• Est. Priority Date: 12/13/2000
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Nelson, Dale H., Sun, Lizhong
• Granted Patent: US 6,552,618 B2
• Time in Patent Office: Days
• US Class Current: 331/11
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A phase-locked loop (PLL) circuit having a voltage-controlled oscillator (VCO) is automatically calibrated for VCO center frequency and VCO gain during power up or responsive to a calibration signal. The VCO has several input voltage versus output frequency operating curves. During a calibration phase, proper VCO center frequency is selected by selecting one of the operating curves. VCO gain is then determined using the selected VCO operating curve. If the value of VCO gain is not within predetermined limits, VCO gain is adjusted accordingly, and the process of selecting a VCO operating curve and determining VCO gain is repeated.

Claims

1. A method for calibrating gain of a voltage controlled oscillator (VCO) in a phase-locked loop (PLL) circuit, said VCO having a plurality of input voltage versus output frequency operating curves, said method comprising the steps of:

(a) selecting one of said plurality of VCO operating curves;

(b) determining VCO gain using values of input voltage and output frequency corresponding to the selected VCO operating curve;

(c) comparing the determined VCO gain with predetermined values of VCO gain; and

(d) if the determined VCO gain is not within the predetermined values of VCO gain, adjusting VCO gain and repeating steps (a) through (c).

2. A method in accordance with claim 1, wherein said step of selecting one of said plurality of VCO operating curves comprises:

applying a sequence of digital control input values to said VCO, wherein each digital control input value corresponds to a different one of said plurality of VCO operating curves; and

selecting one of said sequence of digital control input values responsive to a loop-filter voltage of said PLL circuit.

3. A method in accordance with claim 1, wherein said step of adjusting VCO gain comprises:

applying a sequence of gain digital control values to said VCO, wherein each gain digital control value corresponds to a different value of VCO gain; and

selecting one of said gain digital control values responsive to said determined VCO gain.

4. A method in accordance with claim 3, wherein said step of selecting one of said gain digital control values comprises at least one of incrementing and decrementing said gain digital control value by a least significant bit.

5. An electronic circuit for calibrating gain of a voltage controlled oscillator (VCO) in a phase-locked loop (PLL) circuit, said VCO having a plurality of input voltage versus output frequency operating curves, said electronic circuit comprising:

(a) means for selecting one of said plurality of VCO operating curves;

(b) means for determining VCO gain using values of input voltage and output frequency corresponding to the selected VCO operating curve;

(c) means for comparing the determined VCO gain with predetermined values of VCO gain; and

(d) if the determined VCO gain is not within the predetermined values of VCO gain, means for adjusting VCO gain and repeating (a) through (c).

6. An electronic circuit in accordance with claim 5, wherein said means for selecting one of said plurality of VCO operating curves comprises:

means for applying a sequence of digital control input values to said VCO, wherein each digital control input value corresponds to a different one of said plurality of VCO operating curves; and

means for selecting one of said sequence of digital control input values responsive to a loop-filter voltage of said PLL circuit.

7. An electronic circuit in accordance with claim 5, wherein said means for adjusting VCO gain comprises:

means for applying a sequence of gain digital control values to said VCO, wherein each gain digital control value corresponds to a different value of VCO gain; and

means for selecting one of said gain digital control values responsive to said determined VCO gain.

8. An electronic circuit in accordance with claim 7, wherein said means for selecting one of said gain digital control values comprises at least one of incrementing and decrementing said gain digital control value by a least significant bit.

9. A phase-locked loop (PLL) circuit comprising a voltage controlled oscillator (VCO) for receiving a loop-filter voltage signal and providing a PLL output signal, said VCO having a VCO gain and a VCO center frequency, wherein said VCO gain and said VCO center frequency are automatically calibrated during a calibration phase.

10. A PLL circuit in accordance with claim 9, wherein said PLL circuit is an integrated circuit.

11. A PLL circuit in accordance with claim 9 further comprising a switching configuration, wherein said loop-filter voltage signal is provided to said VCO during normal PLL operations, and a reference voltage is provided to said VCO during said calibration phase.

12. A PLL circuit in accordance with claim 9 further comprising a loop-filter portion for receiving said PLL output signal and an input signal, and for providing said loop-filter voltage signal responsive to a difference in phase between said input signal and a feedback signal, said feedback signal being equal to said PLL output signal divided by N, wherein N is a real number.

13. A PLL circuit in accordance with claim 12 further comprising a VCO center frequency calibration portion for receiving said input signal and said feedback signal, and for providing a center frequency control signal to said VCO for calibrating said VCO center frequency.

14. A PLL circuit in accordance with claim 13 further comprising a VCO gain calibration portion for receiving said center frequency control signal and providing a gain control signal to said VCO for calibrating said VCO gain.

15. A PLL circuit in accordance with claim 14, wherein said VCO gain calibration portion comprises:

a decoder for receiving a trigger signal and providing a decoder output signal;

said trigger signal indicating the completion of an iteration of VCO center frequency calibration;

at least one flip flop for incrementing a value of VCO gain responsive to said decoder output signal; and

a detector for receiving said decoder output signal and for providing a restart signal, wherein said restart signal initiates VCO center frequency calibration.

16. A PLL circuit in accordance with claim 14, wherein said VCO comprises a voltage to current conversion portion for adjusting a transconductance of said voltage to current conversion portion in response to said gain control signal.

17. An integrated circuit having a phase-locked loop (PLL) comprising:

a voltage controlled oscillator (VCO) for receiving a loop-filter voltage signal and providing a PLL output signal, said VCO having a plurality of input voltage versus output frequency operating curves, a VCO gain, and a VCO center frequency, wherein said VCO gain and said VCO center frequency are automatically calibrated during a calibration phase;

a switching configuration, wherein said loop-filter voltage signal is provided to said VCO during normal PLL operations, and a reference voltage is provided to said VCO during said calibration phase;

a loop-filter portion for receiving said PLL output signal and an input signal, and for providing said loop-filter voltage signal responsive to a difference in phase between said input signal and a feedback signal, said feedback signal being equal to said PLL output signal divided by N, wherein N is a real number;

a VCO center frequency calibration portion for receiving said input signal and said feedback signal, and for providing a sequence of center frequency control signals to said VCO for calibrating said VCO center frequency, wherein each one of said sequence of center frequency control signals corresponds to one of said plurality of VCO operating curves; and

a VCO gain calibration portion for receiving said center frequency control signal and providing a sequence of gain control signals to said VCO for calibrating said VCO gain, wherein each one of said sequence of gain control signals corresponds to a different value of VCO gain.