Display apparatus having digital memory cell in pixel and method of driving the same

• US 20020075205A1
• Filed: 11/30/2001
• Published: 06/20/2002
• Est. Priority Date: 11/30/2000
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kimura, Hiroyuki, Maeda, Takashi, Tsunashima, Takanori
• Granted Patent: US 6,778,162 B2
• Time in Patent Office: Days
• US Class Current: 345/55
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0823 used to establish symmetry in driving, e.g. with polarity inversion
• CPC Class Codes: G09G 2300/0833 forming a linear amplifier or follower
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2320/10 Special adaptations of display systems for operation with variable images
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/0428 Gradation resolution change
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Abstract

Disclosed is a circuit constitution of a display apparatus comprising a digital memory (DM) cell for each pixel. The DM cell is composed of one inverter circuit, and a DM switching circuit for controlling an electrical conduction between a pixel electrode and the DM cell is provided. During a normal displaying period, the DM cell and the pixel electrode are not electrically conducted by the DM switching circuit, and a full-color image displaying is performed by dynamic image data supplied to a signal line. During a still image displaying, the DM cell and the pixel electrode are electrically conducted by the DM switching circuit, and a multi-color image displaying is performed by still image data retained in the DM cell.

Claims

1. A display apparatus, comprising:

a first electrode substrate having a plurality of scan lines and a plurality of signal lines arranged so as to intersect with each other;

pixel electrodes, each being arranged at corresponding one of crossing points of said scanning and signal lines;

first capacitor elements, each being electrically in parallel connected to corresponding one of said pixel electrodes; and

first switching elements, each being turned ON/OFF by a row selection signal supplied to the corresponding one of said scan lines, and when turned ON, allowing said signal line and said pixel electrode to be electrically conducted, thus writing video data supplied to said signal line to said pixel electrode,

a second electrode substrate having opposite electrodes, oppositely disposed so as to face the said pixel electrodes with a predetermined gap therebetween;

a display layer sandwiched between said first and second electrode substrates;

a data driver for supplying the video data to said plurality of signal lines in response to one horizontal scanning period; and

a scan driver for sequentially supplying the row selection signal to the corresponding one of said scan lines every said one horizontal scanning period,

wherein said first electrode substrate has;

a digital memory cell composed of one inverter circuit capable of retaining the video data supplied to said signal line; and

a digital memory switching circuit for controlling an electrical conduction between said pixel electrode and said digital memory cell.

2. The display apparatus according to claim 1, wherein said digital memory cell is composed of one inverter circuit and a second capacitor element.

3. The display apparatus according to claim 1, wherein said inverter circuit is composed of a CMOS circuit.

4. The display apparatus according to claim 1, wherein said pixel electrode is a light reflection type pixel electrode constituted by a metallic thin film.

5. The display apparatus according to claim 1, wherein said digital memory switching circuit is composed of a second switching element connected to an input terminal of said digital memory cell, and a third switching element connected to an output terminal of said digital memory cell.

6. The display apparatus according to claim 2, wherein

said digital memory switching circuit is composed of a second switching element connected to an input terminal of said digital memory cell, and a third switching element connected to an output terminal of said digital memory cell, and

said second capacitor element is connected between said second switching element and said inverter circuit.

7. The display apparatus according to claim 5, wherein said second and third switching elements are composed of field effect transistors of the same conductivity type, which are respectively connected to different control signal lines.

8. The display apparatus according to claim 5, wherein said second and third switching elements are composed of field effect transistors of conductivity types different from each other, which are connected to a common control signal line.

9. The display apparatus according to claim 3, wherein third and fourth capacitor elements are connected to the CMOS circuit constituting said inverter circuit.

10. The display apparatus according to claim 1, wherein one of power source wirings of said digital memory cell and a power source wiring for supplying a predetermined voltage to said first capacitor element are shared.

11. The display apparatus according to claim 1, wherein said display layer is a liquid crystal layer.

12. The display apparatus according to claim 1, wherein

during a first displaying period, said pixel electrode and said digital memory cell are not electrically conducted by said digital memory switching circuit, and said first switching element is turned on at a predetermined cycle, thus performing displaying by writing first video data supplied to said signal line to said pixel electrode;

and

during a second displaying period, said pixel electrode and said digital memory cell are electrically conducted by said digital memory switching circuit, said digital memory cell is allowed to retain second video data therein supplied to said signal lines, and then said signal lines and said pixel electrode are not electrically conducted by said first switching element, thus performing displaying by writing the second video data retained in said digital memory cell to said pixel electrode.

13. A method of driving the display apparatus according to claim 12, wherein during said first displaying period, said second switching element alone and said pixel electrode alone are electrically conducted in said digital memory switching circuit.

14. The method of driving the display apparatus according to claim 12, wherein

during said second displaying period, said second and third switching elements are alternately conducted every one frame, the second video data of a different polarity is supplied from said digital memory cell to said pixel electrode every one frame, and a potential of said opposite electrode is inverted in response to a cycle of one frame.

15. The method of driving the display apparatus according to claim 14, wherein during said second displaying period, a turning-on time of said third switching element is made to be longer than that of said second switching element.

16. The method of driving the display apparatus according to claim 12, wherein

during said second displaying period, said pixel electrode and said digital memory cell are electrically conducted by said digital memory switching circuit for each group of a predetermined number of frames, said digital memory cell is allowed to retain the second video data therein supplied to said signal lines, and then said signal lines and said pixel electrode are not electrically conducted by said first switching element, thus performing displaying for each group of a predetermined number of frames by writing the second video data retained in said digital memory cell to said pixel electrode.

17. The method of driving the display apparatus according to claim 16, wherein

during said second displaying period, said digital memory cell is allowed to retain the second video data of a different polarity for a predetermined number of frames, and a potential of said opposite electrode is inverted in response to a cycle of the predetermined number of frames.

18. The method of driving the display apparatus according to claim 14, wherein

a DC power source voltage is supplied to said digital memory cell.

19. The method of driving the display apparatus according to claim 16, wherein

a DC power source voltage is supplied to said digital memory cell.

20. The method of driving the display apparatus according to claim 16, wherein

an AC power source voltage is supplied to said digital memory cell, and a potential of said opposite electrode is inverted in response to a cycle of the AC power source voltage.